Wireless SoC Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Los Angeles, CA
Salary
$175,000–$308,500 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k
This role $242k
$131k most similar roles pay here $327k

This role pays more than 83% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $242k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2321 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1891 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

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As a Wireless SoC Design Engineer, you will join the wireless silicon development team to design CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with architects and IP developers to meet specific power, performance, and area goals while engaging in hardware, software, and power partitioning discussions with firmware and platform engineering teams. Your daily responsibilities include writing micro-architecture and design specifications, coding RTL in SystemVerilog, integrating IP blocks, and optimizing memories and hard macros. You will also perform analysis for area, timing, and power while utilizing industry standard tools for LINT, CDC, and RDC checks. The role requires expertise in SoC architecture, Verilog, AXI/AHB bus fabric, and UPF low-power design techniques to solve complex challenges in the development of advanced wireless silicon components.

Skills

SystemVerilog Verilog ASIC Design SoC Architecture RTL Design Low-Power Design UPF AXI AHB LINT CDC RDC EDA Tools Micro-architecture

What you'll do

  • Write micro-architecture and design specifications for CPU-based subsystems.
  • Code RTL designs using SystemVerilog according to established guidelines.
  • Integrate hardware IP blocks and optimize memories and hard macros.
  • Support verification efforts across multiple levels of the design process.
  • Perform static analysis checks including LINT, CDC, and RDC.
  • Analyze and optimize area, timing, and power metrics for wireless SoCs.
  • Participate in hardware, software, and power partitioning discussions with cross-functional teams.

What we're looking for

  • Bachelor of Science degree with 10+ years of relevant experience.
  • Familiarity with the ASIC design flow.
  • Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
  • Experience writing micro-architecture specifications and converting them to design (preferred).
  • Exposure to design methodologies and industry standard EDA tools (preferred).
  • Experience with AXI/AHB bus fabric and processor sub-systems (preferred).
  • Understanding of UPF and low-power design and implementation techniques (preferred).
  • Self-starter and willingness to learn (preferred).

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