Wireless SoC Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
San Francisco, CA
Salary
$129,300–$225,300 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k
This role $177k
$116k most similar roles pay here $255k

This role pays less than 61% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $177k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2321 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1891 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

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The Wireless SoC Design Engineer joins the wireless silicon development team to design CPU-based subsystems for high performance, low power wireless SoCs. Working within a multi-disciplinary environment, you will collaborate with architects and IP developers to meet specific power, performance, and area goals while engaging in hardware, software, and power partitioning discussions. Your daily responsibilities include writing micro-architecture and design specifications, coding RTL in SystemVerilog, integrating IP blocks, and optimizing memories and hard macros. You will also perform analysis on timing, area, and power while utilizing industry standard tools for LINT, CDC, and RDC checks. The role requires proficiency in Verilog, SoC architecture, AXI/AHB bus fabrics, and UPF low-power design techniques to solve complex integration challenges for advanced wireless products.

Skills

SystemVerilog Verilog ASIC Design SoC Architecture RTL Design Low-Power Design UPF AXI AHB LINT CDC RDC EDA Tools Micro-architecture Digital Design

What you'll do

  • Write micro-architecture and design specifications for CPU-based subsystems.
  • Code RTL designs using SystemVerilog following established guidelines.
  • Integrate IP blocks and optimize memories and hard macros for the block.
  • Support verification efforts across multiple levels of the design process.
  • Perform static analysis checks including LINT, CDC, and RDC.
  • Analyze and optimize area, timing, and power metrics for wireless SoCs.
  • Participate in hardware/software/power partitioning discussions with firmware and platform teams.

What we're looking for

  • Minimum requirement of a bachelor's degree.
  • Familiarity with the ASIC design flow.
  • Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
  • MSEE with some years of industry experience (preferred).
  • Experience writing micro-architecture specifications and converting them to design (preferred).
  • Exposure to design methodologies and industry standard EDA tools (preferred).
  • Experience with AXI/AHB bus fabric and processor sub-systems (preferred).
  • Understanding of UPF and low-power design & implementation techniques (preferred).

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