Wireless SoC Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Francisco, CA
Salary
$184,700–$324,800 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 99% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $255k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2321 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1891 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

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As a Wireless SoC Design Engineer, you will join the wireless silicon development team to design CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with architects and IP developers to meet specific power, performance, and area goals while engaging in hardware, software, and power partitioning discussions. Your daily responsibilities include writing micro-architecture and design specifications, coding in SystemVerilog, integrating IP blocks, and optimizing memories and hard macros. You will also perform analysis on timing, area, and power while utilizing industry standard tools for LINT, CDC, and RDC checks. The role requires expertise in digital design, SoC architecture, Verilog, AXI/AHB bus fabric, and UPF low-power techniques to solve complex integration challenges within the wireless silicon domain, ensuring high-quality designs are delivered through multi-disciplinary collaboration across various engineering fields.

Skills

SystemVerilog Verilog ASIC Design SoC Architecture RTL Design Low-Power Design UPF AXI AHB LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design

What you'll do

  • Write micro-architecture and design specifications for CPU-based subsystems.
  • Code RTL designs in SystemVerilog following established guidelines.
  • Integrate IP blocks and optimize memories and hard macros for the block.
  • Support verification efforts across multiple levels of the design process.
  • Perform static analysis using industry standard tools such as LINT, CDC, and RDC.
  • Analyze and optimize area, timing, and power metrics for wireless SoCs.
  • Participate in hardware/software/power partitioning discussions with firmware and platform teams.

What we're looking for

  • Bachelor's degree and 10+ years of relevant experience.
  • Familiarity with the ASIC design flow.
  • Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
  • Experience writing micro-architecture specifications and converting them to design (preferred).
  • Exposure to design methodologies and industry standard EDA tools (preferred).
  • Experience with AXI/AHB bus fabric and processor sub-systems (preferred).
  • Understanding of UPF and low-power design and implementation techniques (preferred).
  • Self-starter and willingness to learn (preferred).

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