Wireless PHY Design Verification Engineer

What you'll do

• Develop UVM environments and bus functional models for DSP subsystems and IEEE 802.11 protocols.
• Own subsystem verification from initial test planning and environment bring-up through feature closure.
• Build UVM testbench environments, assertions, and infrastructure using DPIs to utilize algorithm models.
• Architect and implement constrained random scenarios to exercise complex protocol interactions.
• Apply data-driven verification closure through coverage tracking, issue tracking, and gap identification.
• Drive verification strategy with cross-functional teams to achieve coverage closure across complex domains.

What we're looking for

• BS degree and a minimum of 10 years of relevant industry experience.
• Track record of several tapeout cycles of sophisticated designs.
• Experience verifying wireless, DSP, or digital communication systems.
• Knowledge of ASIC verification flows with SystemVerilog/UVM, including testbench architecture and coverage-driven methodologies.
• Experience developing verification environments, bringing up complex designs, and debugging simulations.
• Experience with constrained random testing, functional coverage implementation, and assertion-based verification.
• Knowledge of IEEE 802.11 wireless protocols, Bluetooth, Cellular, or similar communication systems (preferred).
• Experience with transaction-level modeling, System models utilizing DPIs, and DSP algorithm verification strategies (preferred).