Wireless PHY Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$122,700–$214,300 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $209k
This role $168k
$106k $280k
below market most similar roles pay here above market

This role pays less than 78% of similar roles. Most pay $177,237–$241,750 — the blue band above. At the midpoint, this role pays about $168k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3498 open roles on FindRole.

Listed pay typically runs $174,200–$277,600 across 2693 roles with salary data.

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At a glance

TL;DR · Wireless PHY Design Verification Engineer

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The Wireless PHY Design Verification Engineer joins the Wireless Connectivity team to ensure first-time-right silicon success for state-of-the-art WiFi SoCs. This role involves verifying sophisticated WiFi PHY digital systems, including time/frequency-domain processing, hardware acceleration, calibration engines, and protocol implementations. You will architect verification strategies for high-rate, low-power, and multi-link wireless features, owning subsystem verification from test planning through coverage closure. Key responsibilities include building UVM environments, bus functional models, assertions, and DPIs to utilize algorithm models. You will implement constrained random scenarios and apply data-driven verification closure using coverage tracking and metrics. Required skills include SystemVerilog, UVM, and ASIC verification flows. The work focuses on solving complex problems in DSP subsystems and IEEE 802.11 protocol implementations for multi-gigabit wireless technology.

Skills

SystemVerilog UVM ASIC Verification IEEE 802.11 DSP Assertion-Based Verification Functional Coverage Bus Functional Models Transaction-Level Modeling Digital Communication Systems Bluetooth Cellular Scoreboarding

What you'll do

  • Develop UVM environments and bus functional models for DSP subsystems and IEEE 802.11 protocols.
  • Own subsystem verification from initial test planning and environment bring-up through feature closure.
  • Build UVM testbench environments, assertions, and infrastructure using DPIs to utilize algorithm models.
  • Architect and implement constrained random scenarios to exercise complex protocol interactions.
  • Apply data-driven verification closure through coverage tracking, issue tracking, and gap identification.
  • Drive verification strategy with cross-functional teams to achieve coverage closure across complex domains.

What we're looking for

  • Minimum requirement of a bachelor’s degree.
  • Track record of several tapeout cycles of sophisticated designs.
  • Experience verifying wireless, DSP, or digital communication systems.
  • Knowledge of ASIC verification flows with SystemVerilog / UVM including testbench architecture, scenario creation, and coverage-driven methodologies.
  • Experience developing verification environments, bringing up complex designs, and debugging simulations.
  • Experience with constrained random testing, functional coverage implementation, and assertion-based verification.
  • Knowledge of IEEE 802.11 wireless protocols, Bluetooth, Cellular, or similar communication systems (preferred).
  • Experience with applying / integrating System models utilizing DPIs (preferred).

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