Low-Power Feature Validation & Bring-Up Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
14 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $186k
This role $216k
$125k most similar roles pay here $279k

This role pays more than 79% of similar roles. Most pay $155,809–$216,062 — the shaded band above. At the midpoint, this role pays about $216k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Low-Power Feature Validation & Bring-Up Engineer

The Low-Power Feature Validation & Bring-Up Engineer joins the Silicon Co-Design Group to develop methodologies and infrastructure for low-power silicon validation and system bring-up on next-generation AI and accelerated computing platforms. You will define power and performance validation strategies, build intelligent workload characterization frameworks using telemetry and behavioral clustering, and develop AI-assisted analytics for anomaly detection and predictive validation. The role involves creating firmware hooks, instrumentation, and automated debug workflows to ensure product readiness across pre-silicon and post-silicon environments. Key technical requirements include expertise in silicon characterization, Windows/Linux low-power states, and power analysis. You will utilize Python, data analytics, and AI/ML tools to build scalable telemetry pipelines and dashboards. This role solves critical challenges in power efficiency and stability by bridging architecture, firmware, and system integration to ensure seamless product release.

What you'll do

  • Define power and performance validation strategies including rail budgets and low-power feature methodologies across product lines.
  • Build workload characterization frameworks using telemetry, behavioral clustering, and AI-assisted analytics to improve coverage.
  • Design instrumentation, counters, and firmware hooks to support scalable silicon observability and automated debug workflows.
  • Bring up and validate system-level low-power features in both pre-silicon and post-silicon environments.
  • Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, and predictive validation analytics.
  • Create automated triage systems and cross-generation debug correlation tools to accelerate productization.
  • Resolve production and feature issues using telemetry-powered insights and scalable debug methodologies for manufacturing teams.

What we're looking for

  • BS/MS in EE, CE, CS, Systems Engineering, or equivalent experience.
  • 10+ years of experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization.
  • Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, and power/performance tradeoffs.
  • Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows for silicon validation and debug.
  • Strong EE fundamentals including digital design, computer architecture, power analysis, statistics, and scripting/programming skills.
  • Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation.
  • Familiarity with AI/LLM-assisted engineering workflows, intelligent automation frameworks, or data-driven debug infrastructure.
  • Proficiency in Python, data analytics, and automation framework development.

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