Low-Power Feature Validation & Bring-Up Engineer

What you'll do

• Define power and performance validation strategies, including power targets, rail budgets, and low-power feature methodologies.
• Build workload characterization frameworks using telemetry, behavioral clustering, and AI-assisted analytics.
• Define instrumentation, counters, and firmware hooks to support scalable silicon observability and automated validation.
• Bring up and validate system-level low-power features across pre-silicon and post-silicon environments.
• Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, and predictive validation analytics.
• Build scalable validation pipelines, intelligent dashboards, and modern engineering workflows for next-generation silicon.
• Resolve production and feature issues using telemetry-powered insights and automated analytics for manufacturing and customer teams.

What we're looking for

• BS/MS in EE, CE, CS, Systems Engineering, or equivalent experience.
• 10+ years of experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization.
• Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, and power/performance tradeoffs.
• Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows for silicon validation, debug, or productization.
• Strong EE fundamentals including digital design, computer architecture, power analysis, statistics, and scripting/programming skills.
• Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation.
• Experience applying AI/ML or LLM technologies to silicon validation, telemetry analytics, workload optimization, or debug automation (preferred).
• Background in platform power management technologies such as S0ix, ASPM, RTD3, or Memory Self Refresh (preferred).