Staff SoC RTL Performance Verification and Emulation Engineer

Arm Holdings

Hybrid Actively hiring
Austin, TX Posted 45 days ago $198,100$268,000 / year

At a glance

AI generated

TL;DR

Arm’s System-on-Chip (SoC) Performance Analysis Team in Central Technology Group is seeking a senior performance verification and emulation engineer to drive architectural improvements and build early analysis platforms for future SoC designs. This role involves performing RTL performance analysis, developing verification plans, and conducting emulator bring-up and execution of complex benchmarks. The ideal candidate will have hands-on experience with hardware emulation platforms, strong system-level debug skills, and a deep understanding of memory systems and interconnect design. Proficiency in Verilog/SystemVerilog, C/C++, and scripting languages like Python is essential, along with expertise in multiprocessor coherency and cache architectures. The team focuses on leveraging AI tools to enhance performance analysis workflows and mentors junior engineers for technical growth.

Skills

Verilog SystemVerilog C C++ Python Ruby Git Subversion Unix/Linux ARM Multiprocessor coherency Mmu Cache architectures Compilers Assembler Device drivers

What you'll do

  • Perform RTL performance analysis and verification for SoC.
  • Implement performance verification plans and debug using simulation/emulation environments.
  • Drive emulation-based performance studies, including emulator bring-up and benchmark execution.
  • Conduct theoretical analysis of memory system optimizations and develop benchmarks.
  • Debug performance failures, identify design bottlenecks, and propose data-driven solutions.

What we're looking for

  • Proven experience in SoC RTL performance analysis and debug using hardware emulation platforms.
  • Hands-on experience with emulator bring-up, configuration, and development of new performance test cases.
  • Strong system-level performance debug skills across complex IP interactions including CPU, GPU, and I/O workloads.
  • Deep understanding of memory system architecture, interconnect design, and multiprocessor coherency.
  • Excellent knowledge of Verilog/SystemVerilog and proficiency in C/C++ with scripting language experience.
  • Strong debugging, data analysis, and technical presentation skills for complex performance issues.
  • Familiarity with ARM architecture, compilers, assemblers, or device drivers preferred.

Market check

Salary context

This $198,100–$268,000 range sits above 82% of similar postings on FindRole.

Peer median band

$152,000$231,000

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$159,937$216,500

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 34 open roles on FindRole.

Listed pay typically runs $184,500–$249,600 across 34 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

More like this

Similar roles

RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, Ca,Us, US 17 days ago $142,200$213,400
Verilog VHDL Perl Python Power management Debugging tools RTL design RISCV CPU architecture High-performance systems Low-power microarchitecture Telemetry architecture Interrupt controller Timer synchronization RAS and safety mechanisms Architecture and performance monitoring Scripting languages Simulation tools Waveform debugging tools

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, Ca,Us, US 23 days ago $167,100$250,700
Verilog VHDL Perl Python RTL Microarchitecture Instruction_fetch_and_decode Branch_prediction Out_of_order_execution Integer_and_floating_point_execution Load_store_execution Prefetching Cache_and_memory_subsystems Logic_design_principles Timing_and_power_implications Low_power_microarchitecture_techniques

CPU RTL Methodology Engineer

Qualcomm

Santa Clara, Ca,Us, US 55 days ago $198,700$298,100
Python Git Verilog SystemVerilog TCL Perl Bash CI/CD CAD RTL

CPU Systems RTL Engineer

Qualcomm

Santa Clara, Ca,Us, US 17 days ago $167,100$250,700
C C++ Python Perl Verilog VHDL UVM SystemC Cadence Synopsys ModelSim Questa TCL SV CI/CD

CPU Micro-Architect RTL Engineer

Qualcomm

Austin, Tx,Us, US 23 days ago $154,000$231,000
RISC-V RTL Verilog SystemC VHDL Processor pipelines Out-of-order execution Load/store units Caches Cache coherence Memory hierarchy Multi-processor systems Multi-threaded systems Low-power design Performance optimization Area and timing goals Communication skills Collaboration skills Teamwork skills

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, Ca,Us, US 23 days ago $127,200$190,800
SystemVerilog RTL Verilog Linting CDC LEC CLP Processor integration Bus interface Cache Digital design Logic design