Staff SOC Performance Architect

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$198,100–$268,000 / yr
Posted
20 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $212k
This role $233k
$154k most similar roles pay here $280k

This role pays more than 67% of similar roles. Most pay $182,000–$242,200 — the shaded band above. At the midpoint, this role pays about $233k versus about $212k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Staff SOC Performance Architect

As a Staff SOC Performance Architect, you will join a collaborative team to shape the next generation of high-performance interconnect IP for infrastructure, automotive, and mobile markets. You will work alongside micro-architects, RTL, and validation engineers to develop cycle-accurate timing and performance models for coherent and non-coherent interconnects. Your daily responsibilities include driving new feature development by evaluating architectural trade-offs, building well-correlated performance models for internal and customer use, designing test suites, and identifying system bottlenecks. To succeed in this role, you must possess a strong foundation in computer architecture and microarchitecture, along with proven experience in SoC performance modeling or RTL within the semiconductor industry. Required technical skills include C++ for large-scale software development, SystemC TLM, and Python scripting. Knowledge of PCIe, CHI protocols, and performance verification methodologies is also highly valued.

What you'll do

  • Develop cycle-accurate timing and performance models for coherent and non-coherent interconnects.
  • Evaluate architectural trade-offs to drive the development of new features.
  • Build high-quality, well-correlated performance models for internal analysis and customer evaluation.
  • Provide technical collateral and insights to customers to help them build high-performing systems.
  • Design performance test suites to identify system bottlenecks and validate expectations.
  • Propose data-driven solutions to improve overall system performance.

What we're looking for

  • Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or Computer Science.
  • Proven experience in SoC performance modeling and/or RTL within the semiconductor industry.
  • Proven track record of developing cycle-accurate performance models and evaluating microarchitectural features.
  • Strong C++ skills for large-scale software development.
  • Experience with SystemC TLM and proficiency in Python scripting.
  • Knowledge of interconnect microarchitecture, PCIe, and CHI protocols (preferred).
  • Familiarity with realistic workloads used for system performance optimization (preferred).
  • Experience with performance verification methodologies and correlating software models with RTL (preferred).

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