Staff Engineer, PCIe PHY/Link Analysis

What you'll do

• Analyze and integrate the PCIe protocol stack from the Physical Layer through the Transaction/Transport Layer.
• Manage link training, equalization sequencing, and configuration-space flows during device bring-up.
• Validate TLP/DLLP handling, flow control, credit management, and end-to-end data integrity across the stack.
• Debug complex PHY, Link, and Transport layer issues for NVMe SSD products from Gen1 to Gen7.
• Support industry PHY/Link compliance tests and participate in PCI-SIG events.
• Provide onsite technical support for PHY/Link related tasks at customer sites and labs.

What we're looking for

• A BS in Engineering or Computer Science and 8 years of experience, or an MS in Engineering or Computer Science and 5 years of experience is required.
• Deep proficiency with the PCIe protocol stack from the Physical Layer through the Data Link and Transaction/Transport Layers is required.
• Strong hands-on knowledge of LTSSM, link training, equalization, flow control, and error handling (AER) is required.
• Working knowledge of PHY-layer operations to root-cause issues across the PHY/Link boundary is required.
• Solid experience in C/C++ for embedded systems and expertise with UART/JTAG/ICE debuggers is required.
• Experience using PCIe protocol analyzers, logic analyzers, and signal analyzers for link and transaction-level debug is required.
• Knowledge of SI/PI for PCIe is preferred.
• Proficiency in NVMe, CXL, or SAS/SATA protocols; experience in SoC validation; and knowledge of PCIe power management are preferred.