Staff Engineer, PCIe PHY/Link Analysis

What you'll do

• Analyze and integrate the PCIe protocol stack from the Physical Layer through the Transaction/Transport Layer.
• Own LTSSM behavior, link training, equalization sequencing, and PCIe enumeration during device bring-up.
• Validate TLP/DLLP handling, flow control, credit management, and end-to-end data integrity.
• Debug complex PHY, Link, and Transport layer issues for NVMe SSD products from Gen1 to Gen7.
• Support industry PHY/Link compliance tests and participate in PCI-SIG events.
• Provide onsite technical support for PHY/Link related tasks at customer sites and labs.

What we're looking for

• BS in Computer/Electrical/Electronic Engineering or Computer Science with 8+ years of relevant experience is required.
• MS in Computer/Electrical/Electronic Engineering or Computer Science with 5+ years of relevant experience is required.
• Deep proficiency in the full PCIe protocol stack from the Physical Layer through the Transaction/Transport Layer is required.
• Strong hands-on knowledge of LTSSM, link training/equalization, PCIe enumeration, flow control, replay/retry, and error handling (AER) is required.
• Working knowledge of PHY-layer operations (CDR to Equalizer such as VGA, CTLE, DFE, FFE, DSP, etc.) is required.
• Solid experience in C/C++ for embedded systems and expertise with UART/JTAG/ICE debuggers is required.
• Strong experience with PCIe protocol analyzers, logic analyzers, and signal analyzers is required.
• Knowledge of SI/PI for PCIe, NVMe, CXL, SAS/SATA, SoC validation, and PCIe power management is preferred.