Staff Bench Test Engineer

Qualcomm

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $151,900–$227,900 / yr
Posted: 9 days ago
Closes: Dec 1, 2026
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $190k

$131k most similar roles pay here $241k

This role pays more than 53% of similar roles. Most pay $162,025–$221,500 — the shaded band above. At the midpoint, this role pays about $190k versus about $192k for comparable roles.

Based on 239 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 660 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

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At a glance

TL;DR · Staff Bench Test Engineer

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The Post Silicon Engineering group at Qualcomm Connectivity & Networking seeks a senior engineer to develop and execute test methodologies for characterizing WLAN SOCs and related components such as FE modules, PLLs, ADCs, DACs, and high-speed interfaces like PCIe, USB3, MIPI. This role involves optimizing design parameters, validating specification compliance, and driving initial silicon bring-up and debug while collaborating closely with cross-functional teams throughout the product lifecycle. The ideal candidate will have hands-on experience with lab equipment including oscilloscopes, J-BERTs, TDRs, spectrum analyzers, and scripting languages like Python or .NET C#. Familiarity with RF, mixed-signal, digital test methods, and wireless standards such as WLAN, UWB, GPS, FM, and Bluetooth is preferred.

Skills

Python .NET C# PCIe USB3 MIPI DDR WLAN UWB GPS Bluetooth Oscilloscopes J-BERT TDR Spectrum Analyzers Vector-Signal Transceivers Logic Analyzers Network Analyzers Noise Source RF mixed-signal digital test methods

What you'll do

Define and execute test methodologies for WLAN SOCs.
Characterize RF components like Transceivers, FEMs, PLLs, ADCs, DACs.
Validate high-speed interfaces such as PCIe, USB3, MIPI in silicon bring-up.
Assist in HW design and debug power integrity and signal integrity issues.
Provide failure mode analysis and corrective actions for test failures.

What we're looking for

Minimum MS in Electrical Engineering with 6 years of experience or BS in Electrical Engineering with 10 years of experience.
Experience developing and executing test methodologies for WLAN SOCs and related components.
Hands-on lab equipment expertise including Oscilloscopes, J-BERT, TDR, Spectrum Analyzers, Vector-Signal Transceivers.
Familiarity with RF, mixed-signal, digital test methods, and scripting languages like Python or .NET C#.
Knowledge of high-speed IO board design concepts and protocols such as PCIe/USB/MIPI/DDR.
Strong problem-solving skills for debugging power integrity and signal integrity issues.

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