SoC UPF Methodology Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $142,300–$263,300 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $210k

This role $203k

$127k $283k

below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $177,250–$241,750 — the blue band above. At the midpoint, this role pays about $203k versus about $210k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SoC UPF Methodology Engineer

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The SoC UPF Methodology Engineer joins the Low Power group to develop capabilities for low-power chip design. This role involves refining the Unified Power Format framework, enhancing power intent specification, and ensuring seamless integration and rigorous verification across mobile products. Key responsibilities include developing tailored UPF solutions, overseeing deployment and sign-off for frontend and place-and-route stages, and conducting power intent assessments on custom circuitry. The engineer will also explore integrating AI/ML technologies to optimize UPF processes. Required skills include expertise in UPF implementation and verification, proficiency in Python and Tcl scripting, and knowledge of CMOS power design principles. The role utilizes multi-voltage static verification tools like VSILP/VCLP and CLP to solve power intent challenges within the RTL-to-GDSII design flow for mobile SOCs.

Skills

UPF RTL-to-GDSII Python Tcl AI/ML Static Verification Dynamic Verification CMOS Power Design VSILP VCLP CLP Power Intent place-and-route ERC Sign-off

What you'll do

Enhance power intent coverage using advanced static and dynamic verification techniques.
Develop tailored UPF solutions to meet specific project requirements.
Oversee UPF deployment and sign-off for frontend and place-and-route stages.
Conduct thorough power intent assessments on custom circuitry.
Integrate AI/ML technologies to optimize UPF processes and methodologies.
Troubleshoot and fix UPF-related workflow challenges for design and verification teams.
Drive transistor level power ERC sign-off and power intent implementation on mobile SOCs.

What we're looking for

A bachelor's degree in a relevant field is required.
At least 3 years of relevant industry experience is required.
Expertise in UPF implementation and verification (preferred).
Proficiency in scripting with languages like Python and Tcl (preferred).
Understanding of CMOS power design principles (preferred).
Experience applying AI/ML to coding and workflow optimization (preferred).
Knowledge of multi-voltage static verification tools such as VSILP/VCLP or CLP (preferred).
Familiarity with the complete RTL-to-GDSII design flow (preferred).

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