SoC UPF Methodology Engineer

Apple Inc

Confirmed live today Low trust

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Work type: On-site
Location: Austin, TX
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

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At a glance

TL;DR · SoC UPF Methodology Engineer

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The SoC UPF Methodology Engineer joins the Low Power group to develop capabilities for low-power chip design. This role focuses on refining the Unified Power Format framework to support state-of-the-art mobile SOCs. Key responsibilities include enhancing power intent coverage through static and dynamic verification, developing tailored UPF solutions for specific project requirements, and overseeing deployment and sign-off for frontend and place-and-route stages. The engineer will conduct power intent assessments on custom circuitry and troubleshoot workflow challenges with multidisciplinary teams. Technical requirements include proficiency in Python and Tcl scripting, knowledge of CMOS power design principles, and experience with multi-voltage static verification tools like VSILP, VCLP, and CLP. Additionally, the role involves integrating AI/ML technologies to optimize UPF processes and methodologies within the RTL-to-GDSII design flow.

Skills

UPF Power Intent Python Tcl AI/ML RTL-to-GDSII Static Verification Dynamic Verification CMOS Power Design VSILP VCLP CLP Power ERC place-and-route

What you'll do

Enhance power intent coverage using advanced static and dynamic verification techniques.
Develop tailored UPF solutions to meet unique project requirements.
Oversee UPF deployment and sign-off for frontend and place-and-route stages.
Conduct thorough power intent assessments on custom circuitry.
Integrate AI/ML technologies to optimize UPF processes and methodologies.
Troubleshoot and fix UPF-related workflow challenges with design and verification teams.
Drive transistor level power ERC sign-off and power intent implementation on mobile SOCs.

What we're looking for

A bachelor's degree in a relevant field is required.
A minimum of 3 years of relevant industry experience is required.
Expertise in UPF implementation and verification (preferred).
Proficiency in scripting with languages like Python and Tcl (preferred).
Understanding of CMOS power design principles (preferred).
Experience applying AI/ML to coding and workflow optimization (preferred).
Knowledge of multi-voltage static verification tools such as VSILP/VCLP or CLP (preferred).
Familiarity with the complete RTL-to-GDSII design flow (preferred).

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