SoC UPF Methodology Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $184,700–$324,800 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k

This role $255k

$139k $345k

below market most similar roles pay here above market

This role pays more than 92% of similar roles. Most pay $177,250–$241,750 — the blue band above. At the midpoint, this role pays about $255k versus about $210k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SoC UPF Methodology Engineer

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The SoC UPF Methodology Engineer joins the Low Power group to develop capabilities for low-power chip design. This role focuses on enhancing Unified Power Format methodologies by refining power intent specification, execution, and validation for mobile SOCs. Key responsibilities include developing tailored UPF solutions, overseeing deployment and sign-off for frontend and place-and-route stages, and conducting power intent assessments on custom circuitry. The engineer will integrate AI/ML technologies to optimize workflows and troubleshoot challenges with design and verification teams. Required skills include expertise in UPF implementation, CMOS power design principles, and the RTL-to-GDSII design flow. Candidates should be proficient in Python and Tcl scripting and possess knowledge of multi-voltage static verification tools such as VSILP, VCLP, and CLP to ensure rigorous verification across mobile products.

Skills

UPF Python Tcl AI/ML RTL-to-GDSII Static Verification Dynamic Verification CMOS VSILP VCLP CLP Power Intent Place-and-Route

What you'll do

Enhance power intent coverage using advanced static and dynamic verification techniques.
Develop tailored UPF solutions to meet unique project requirements.
Oversee UPF deployment and sign-off for frontend and place-and-route stages.
Conduct thorough power intent assessments on custom circuitry.
Troubleshoot and fix UPF-related workflow challenges with design and verification teams.
Integrate AI/ML technologies to optimize UPF processes and methodologies.

What we're looking for

A bachelor's degree in a relevant field is required.
At least 10 years of relevant industry experience is required.
Expertise in UPF implementation and verification (preferred).
Proficiency in scripting with languages like Python and Tcl (preferred).
Understanding of CMOS power design principles (preferred).
Experience applying AI/ML to coding and workflow optimization (preferred).
Knowledge of multi-voltage static verification tools such as VSILP/VCLP or CLP (preferred).
Familiarity with the complete RTL-to-GDSII design flow (preferred).

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