SoC Physical Design Engineer, PnR

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$129,300–$194,700 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $204k
This role $162k
$113k $281k
below market most similar roles pay here above market

This role pays less than 82% of similar roles. Most pay $177,250–$231,187 — the blue band above. At the midpoint, this role pays about $162k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Engineer, PnR

Role Posting Log in to save

JOB TITLE: SoC Physical Design Engineer, PnR The SoC Physical Design Engineer, PnR will join the hardware team to manage the physical implementation of design partitions from netlist to tapeout for a highly complex SOC using innovative process technology. This role involves collaborating with architecture, CAD, timing, and logic design teams to drive physical aspects early in the design cycle. Key responsibilities include completing netlist to GDS2 implementation, performing timing, physical, and electrical verification, and driving signoff closure. The candidate must possess knowledge of chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route, power grid, timing, and physical design verification. Required skills include understanding logic gates, while preferred experience includes Verilog, VHDL, Python, Perl, TCL, and SPICE for resolving design and flow issues.

Skills

PnR Physical Design VLSI Verilog VHDL Python Perl TCL SPICE STA DRC LVS EMIR Redhawk Totem Voltus GDS2 Floor-planning Physical Synthesis

What you'll do

  • Execute the physical implementation of design partitions from netlist to tapeout.
  • Complete netlist to GDS2 implementation while meeting specific schedule and design goals.
  • Drive timing, physical, and electrical verification to achieve signoff closure for partitions.
  • Coordinate with logic design teams to understand partition architecture and drive physical aspects early.
  • Resolve and improve design and flow issues related to the physical design process.
  • Identify potential solutions for technical bottlenecks and drive execution of those solutions.

What we're looking for

  • BS degree with 0+ years of experience.
  • Basic understanding of logic gates.
  • Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route, power grid, timing, and physical design verification.
  • Knowledge of EMIR (Redhawk/Totem/Voltus).
  • Previous internship, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design (preferred).
  • Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields (preferred).
  • Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE (preferred).

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