As a Senior VLSI Methodology Engineer at NVIDIA, you will join the Physical Design team to architect and integrate data-driven pipelines and verification systems that power library modeling and quality checks for advanced graphics processors and SOC libraries. Your day-to-day responsibilities include developing automated flows and tools using modern scripting languages and industry-standard EDA tools such as Synopsys Design Compiler, Siemens Calibre, and Cadence Virtuoso, while collaborating with design teams to enhance cell design methodologies and ensure system-level quality and robustness. You will need advanced programming skills in Python, C++, or Perl, along with experience in workflow automation and software architecture for data pipelines. The role requires a deep understanding of chip design flows and hierarchical approaches, as well as proven expertise in library modeling, quality systems, and physical design automation, including the use of AI and machine learning to enhance EDA tools and methodologies.
Skills
Python
C++
Perl
Synopsys Design Compiler
Siemens Calibre
Cadence Virtuoso
EDA tools
AI
machine learning
LLMs
workflow automation
data pipelines
software architecture
chip design flows
library modeling
quality systems
physical design automation
hierarchical approaches
top-down approaches
What you'll do
Develop scalable systems and methodologies for physical design quality checking.
Build automated flows and tools for library analysis using modern scripting languages.
Integrate library quality systems with design teams, focusing on adaptive threshold partitioning.
Define guidelines for library modeling, abstraction, and data integrity standards.
Enhance EDA tool automation through AI and machine learning integration.
What we're looking for
M.S. in Electrical Engineering or related field and 4+ years of Physical Design and CAD methodology experience
Direct development experience with industry-standard EDA tools, including scripting and customization
Advanced programming skills in Python, C++, or Perl for workflow automation and data pipeline development
Proven understanding of chip design flows and hierarchical approaches
2+ years in library modeling, quality systems, or physical design automation
Strong experience in developing and maintaining robust library models with system-level quality focus
Demonstrated use of AI, machine learning, or LLMs to enhance EDA tools and methodologies
Market check
Salary context
This
$136,000–$218,500
range sits above
49%
of similar postings on FindRole.
Peer median band
$148,500–$218,850
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$156,000–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.*
* 240 is the maximum number of comparable postings sampled.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
802 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 798 roles with salary data.
Us, Ca, Santa Clara, US58 days ago
$168,000–$264,500
C++
Python
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GUI development
Machine learning
VLSI Physical Design
Us, Ca, Santa Clara, US58 days ago
$168,000–$264,500
C++
Verilog
SystemVerilog
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AI
ML
GNNs
RL
DFT
clock distribution
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congestion
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SAT solvers
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high performance computing
multithreading
distributed computing