We are seeking an EDA Software R&D Engineer with a focus on RTL synthesis and digital logic optimization to join our cutting-edge team at a leading hardware company. This role involves inventing new algorithms for graph-based analysis and manipulation, developing physical-aware synthesis techniques using placement feedback, and rapidly analyzing the impact of RTL changes on timing and power. You will also prototype machine learning methods like GNNs and RL to guide optimization decisions and integrate them into production. Ideal candidates have a strong background in Electrical Engineering or Computer Science with extensive experience in EDA software and VLSI flows, particularly in logic synthesis and digital optimization. Proficiency in modern C++ (templates/STL, concurrency libraries), RTL design concepts, and high-performance software design is essential. Experience with tools like Verific for parsing and Espresso for minimization, as well as knowledge of SAT solvers and combinatorial optimization techniques, will be highly valued. This role offers unparalleled intellectual freedom to explore broad technical areas and directly impact the world’s best AI hardware designs.
Skills
C++
Verilog
SystemVerilog
EDA
RTL synthesis
digital logic optimization
graph-based algorithms
AI
ML
GNNs
RL
DFT
clock distribution
power gating
placement
congestion
timing analysis
SAT solvers
technology mapping
clustering
min cost tree covering
high performance computing
multithreading
distributed computing
What you'll do
Invent and develop new algorithms for RTL synthesis and digital logic optimization.
Build physical-aware synthesis techniques using placement/congestion/timing feedback to enhance PPA.
Develop strategies to analyze RTL changes' impact on timing, power, area, DFT, clocking, and power delivery.
Prototype and integrate machine learning methods like GNNs and RL into production for optimization guidance.
Explore high-performance algorithms for clustering, min cost tree covering, and efficient technology mapping in logic synthesis.
What we're looking for
MS or PhD in Electrical Engineering or Computer Science or equivalent experience with 6+ years in EDA software and VLSI flows.
Expertise in logic synthesis, global routing, static timing analysis, power optimization, and SAT solvers.
Strong C++ skills including templates/STL, concurrency libraries, profiling, performance optimization, data structures, algorithms, and testing.
Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts like timing, clocking, DFT basics, and power intent.
Experience with EDA building blocks such as Verific for parsing, Espresso for minimization, and components for logic rewriting and combinatorial optimization.
Proficiency in high performance software design including multithreading, distributed computing, efficient memory management, and I/O use.
Market check
Salary context
Above market
How this pay compares to similar roles
Similar $176k
This role $216k
$111k
most similar roles pay here
$281k
This role pays more than
81%
of similar roles. Most pay
$142,400–$210,093
— the shaded band above.
At the midpoint, this role pays about
$216k
versus about
$176k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
824 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 812 roles with salary data.
C++
EDA
RTL synthesis
digital logic optimization
graph-based algorithms
AI
ML
GNNs
RL
high performance computing
multithreading
distributed computing
Verilog
SystemVerilog
static timing analysis
power & area optimization
SAT solvers
Verific
Espresso
C++
Python
ICCAD tools
Innovus
Computational geometry
Graph theory
Algorithm development
Multithreading
Distributed computing
High performance software design
GUI development
Machine learning
VLSI Physical Design