Senior SoC Architect, RAS

Nvidia

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Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXHillsboro, OR
Salary
$184,000–$287,500 / yr
Employment
Full-time
Posted
55 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k
This role $236k
$150k $302k
below market most similar roles pay here above market

This role pays more than 74% of similar roles. Most pay $165,150–$241,750 — the blue band above. At the midpoint, this role pays about $236k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior SoC Architect, RAS

The Senior SoC Architect, RAS joins the team to define and deliver Reliability, Availability, and Serviceability hardware architecture for Tegra System-on-Chips. This role involves driving RAS features from early architectural concepts through design implementation, verification, validation, and production readiness. You will define requirements for fault detection, correction, containment, telemetry, and recovery across CPUs, interconnects, memory systems, and IOs. Key responsibilities include creating hardware specifications, error-handling flows, and architectural models using SystemC, C/C++, and Python. You will collaborate with firmware and software partners to ensure features are debuggable and aligned with system-level requirements. The work addresses technical challenges in high-reliability environments, including space and radiation-aware designs where single-event effects or memory corruption can impact system reliability across autonomous vehicles and edge systems.

What you'll do

  • Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, and IOs.
  • Own RAS features from initial concept through architecture specification, RTL implementation, and production readiness.
  • Develop architectural requirements for fault detection, correction, containment, telemetry, and recovery mechanisms.
  • Create hardware specifications, error-handling flows, and architectural models using SystemC, C/C++, or Python.
  • Plan and review verification strategies including error injection, recovery validation, and resiliency modeling.
  • Perform failure analysis and silicon debug for lab, post-silicon, production, and field findings.
  • Apply RAS principles to high-reliability environments, including space-aware and radiation-aware use cases.
  • Patent novel hardware architecture techniques to improve system resiliency, observability, and serviceability.

What we're looking for

  • MS or PhD degree in computer engineering, electrical engineering, or equivalent experience.
  • At least 8+ years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience.
  • Strong understanding of SoC Reliability, Availability, and Serviceability (RAS) including fault detection, correction, telemetry, and recovery.
  • Experience defining and driving hardware architecture features through the full development lifecycle from concept to production readiness.
  • Strong understanding of overall SoC architecture including micro-architecture, full-chip integration, firmware interfaces, and platform flows.
  • Meaningful industry expertise in areas such as safety, debug, clocks, resets, interconnects, memory controllers, or IO technologies.
  • Hands-on experience with design verification, silicon validation, fault injection, coverage analysis, resiliency modeling, or reliability validation methodology.
  • Familiarity with radiation effects, space operation, or other high-reliability deployment environments (preferred).

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