Senior Silicon Product Development Engineer

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$258,750 / yr
Posted
22 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $185k
This role $213k
$128k most similar roles pay here $273k

This role pays more than 72% of similar roles. Most pay $152,955–$216,250 — the shaded band above. At the midpoint, this role pays about $213k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 985 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 971 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Silicon Product Development Engineer

As a Senior Silicon Product Development Engineer at NVIDIA, you will join a world-class team focused on launching cutting-edge Data Center products. Your primary responsibilities include developing ATE test content, optimizing GPU manufacturing yields, and predicting test durations to enhance product quality. You will also manage vendor relationships with Foundry, Assembly, and Memory vendors, ensuring seamless collaboration for flawless delivery. This role demands expertise in ASIC Mixed Signal build, characterization, and qualification of BIST and SCAN DFT methodologies, along with knowledge of advanced Silicon Process technology such as FinFET. Proficiency in Chip-On-Wafer-On-Substrate Assembly, HBM Memory vendor management, and comprehensive understanding of silicon failure analysis techniques are essential. This position offers a unique opportunity to impact the quality and performance of NVIDIA’s groundbreaking silicon products at scale.

What you'll do

  • Own development and implementation of ATE test content for GPU product line.
  • Minimize excess costs by accurately predicting test durations and analyzing outcomes.
  • Develop and maintain failure analysis plans to improve manufacturing yields.
  • Manage key vendor relationships, especially with Foundry, Assembly, and Memory vendors.
  • Collaborate closely with Supply and Demand program management to ensure chip quality.

What we're looking for

  • 7+ years of direct PDE experience in ASIC Mixed Signal build and qualification.
  • Strong problem-solving skills with expertise in BIST and SCAN DFT methodologies.
  • Knowledgeable in advanced Silicon Process technology including FinFET.
  • Hands-on experience in Chip-On-Wafer-On-Substrate Assembly and HBM Memory vendor management.
  • Comprehensive understanding of silicon characterization, wafer sort, and final test DFT coverage.

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