Senior Silicon Reliability Engineer

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
16 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k
This role $216k
$121k most similar roles pay here $280k

This role pays more than 84% of similar roles. Most pay $157,125–$210,656 — the shaded band above. At the midpoint, this role pays about $216k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior Silicon Reliability Engineer

NVIDIA is seeking a senior Silicon Reliability Engineer to join its cutting-edge technology team, focusing on ensuring the world-class reliability of high-performance products. This role involves collaborating closely with wafer foundries and internal teams like Design and Advanced Technology Group to establish process reliability requirements for new technology nodes and support product bring-ups. The engineer will drive test vehicle qualifications, perform wearout assessments, provide design guidance, and develop reliability methodologies to optimize performance. Key responsibilities include planning stress tests, building failure models, and assessing excursion materials with foundries. Ideal candidates possess a deep understanding of semiconductor process technologies, reliability physics, and statistical tools like JMP, along with expertise in various failure mechanisms and industry standards such as JEDEC and AEC.

What you'll do

  • Develop process reliability requirements for new technology nodes with wafer foundries and internal teams.
  • Drive test vehicle qualifications and improve process reliability before product taping out and bring-up.
  • Perform wearout reliability assessments to provide guidance on Design for Reliability for next generation products.
  • Provide Vmax, aging guardband guidelines and develop methodologies to optimize product reliability performance.
  • Plan and perform stress tests with foundries to build reliability models for extrinsic failure mechanisms.

What we're looking for

  • Deep understanding of cutting-edge semiconductor process technologies and reliability physics.
  • Expertise in wearout failure mechanisms, wafer level reliability tests, and industry standards.
  • Proficient in reliability statistics and failure rate calculations across different life periods.
  • Knowledge of semiconductor defects, root causes, and defect screening methodologies.
  • Hands-on experience with reliability data analysis using statistical tools like JMP.

More like this

Similar roles

Senior Silicon Product Development Engineer

Nvidia

Santa Clara, CA 45 days ago $168,000$258,750
ASIC BIST SCAN_DFT FinFET Chip_On_Wafer_On_Substrate_Assembly HBM_Memory Memory_testing_methodology Assembly_stacking_processes Vendor_management GPU_characterization Wafer_test_DFT_coverage Final_test_DFT_coverage

Senior Circuit Characterization Engineer

Nvidia

Santa Clara, CA 4 days ago $136,000$218,500
Python C C++ Linux Silicon Bringup Frequency Characterization Power Characterization Tester to System Correlation Lab Equipment Usage Product Binning Data Analysis Critical Path Analysis Power Supply Noise Analysis Substrate Noise Mitigation Digital Design BIOS Drivers Software Applications
Hybrid

Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA 17 days ago $136,000$218,500
Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence
Hybrid

Senior IC Design Engineer

Medtronic

Mounds View North, MN 9 days ago $108,000$162,000
SystemVerilog UVM Python TcL Perl Cadence Genus Cadence Conformal Cadence Innovus Cadence Voltus Cadence Tempus Cadence Modus Low power design methods DSP Digital Analog Boundary (DAB) crossings A2D D2A Lab automation methods Agentic AI
Hybrid

Senior Hardware Validation Engineer

Nvidia

Santa Clara, CA 148 days ago $136,000$212,750
Python C/C++ JavaScript AWS Kubernetes Terraform CI/CD PostgreSQL Docker Prometheus Grafana x86 Arm GPU Networking Storage Deep Learning AI Applications Oscilloscopes Digital Multi Meter