Senior Silicon Product Development Engineer

Nvidia

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$258,750 / yr
Posted: 45 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k

This role $213k

$122k most similar roles pay here $273k

This role pays more than 71% of similar roles. Most pay $152,591–$216,250 — the shaded band above. At the midpoint, this role pays about $213k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior Silicon Product Development Engineer

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NVIDIA seeks a Senior Silicon Product Development Engineer to join its GPU PDE team, where you will manage the product bring-up process from pre-Silicon through NPI launch. This role involves developing ATE test content, maintaining project plans to meet market delivery timelines, and collaborating with Foundry, Assembly, and Memory vendors to ensure flawless execution. You will also predict test durations, analyze characterization outcomes, and work closely with Supply and Demand program management to exceed chip quality levels. Ideal candidates have a Bachelor or Master's degree in Electrical or Computer Engineering, 7+ years of PDE experience, expertise in ASIC Mixed Signal build and qualification, knowledge of FinFET technology, and hands-on experience with Chip-On-Wafer-On-Substrate Assembly and HBM Memory vendor management.

Skills

ASIC BIST SCAN_DFT FinFET Chip_On_Wafer_On_Substrate_Assembly HBM_Memory Memory_testing_methodology Assembly_stacking_processes Vendor_management GPU_characterization Wafer_test_DFT_coverage Final_test_DFT_coverage

What you'll do

Own the development and implementation of ATE test content for product line.
Develop and maintain project plans to adhere to market delivery timelines strictly.
Manage key vendor relationships with Foundry, Assembly, and Memory vendors.
Impact manufacturing yields by accurately predicting test durations and analyzing outcomes.
Collaborate closely with Supply and Demand program management to meet chip quality levels.

What we're looking for

7+ years of direct PDE experience with ASIC Mixed Signal build and qualification.
Strong problem-solving skills and expertise in BIST and SCAN DFT methodologies.
Knowledgeable in advanced Silicon Process technology like FinFET.
Hands-on experience in Chip-On-Wafer-On-Substrate Assembly and HBM Memory vendor management.
Comprehensive understanding of memory testing methodology and assembly stacking processes.

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