NVIDIA seeks a Senior Power Integrity Engineer to join its LPU Packaging team, where you will define best-in-class power delivery design practices from die/package through rack levels for GPUs and other high-performance products. Your responsibilities include owning the PI specification, architecting package-level PDNs, driving system-level PI design, performing simulations with industry-standard tools like PowerSI and Sigrity, generating reusable models, and executing lab validation plans to ensure compliance with specifications. The ideal candidate has a strong background in power integrity for large GPUs or CPUs, hands-on experience with FCBGA and 25D/3D integration, proficiency in frequency-domain PDN impedance analysis tools, and expertise in board-level PDN design. Additionally, you should have demonstrated leadership in end-to-end PI for major GPU programs and a deep understanding of rack-level power distribution in data centers. This role involves working on cutting-edge technologies in AI, Deep Learning, Autonomous Vehicles, and Robotics, requiring strong communication skills to explain complex trade-offs to technical teams and stakeholders.
Define best-in-class power delivery design practices from die/package through rack levels.
Own PI specification and methodology, setting PDN targets for GPU, HBM, and high-speed interfaces.
Architect package-level PDNs by collaborating on bump/ball maps and decoupling strategies.
Drive system-level PI design, including board-level PDN planning and VRM interface optimization.
Perform PI extraction and simulation for advanced packages using industry-standard tools.
What we're looking for
MS or PhD in Electrical Engineering or related field with 12+ years of Power Integrity experience
Strong background in power integrity for high-current, low-voltage rails within large GPUs, ASICs, or CPUs
Proven ownership and hands-on experience in chip-package-board PDN design and sign-off process
Proficiency with frequency-domain PDN impedance analysis and time-domain transient/droop simulation tools
Deep understanding of board-level PDN design including stack-up definition and VRM placement on high-layer-count boards
Experience executing lab measurements to correlate measured noise and droop to original specifications
Demonstrated leadership in end-to-end PI for a major GPU, CPU, or ASIC program from concept through mass production
Market check
Salary context
Above market
How this pay compares to similar roles
Similar $172k
This role $253k
$112k
most similar roles pay here
$332k
This role pays more than
96%
of similar roles. Most pay
$138,825–$205,000
— the shaded band above.
At the midpoint, this role pays about
$253k
versus about
$172k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
824 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 812 roles with salary data.
Python
C
C++
Linux
Silicon Bringup
Frequency Characterization
Power Characterization
Tester to System Correlation
Lab Equipment Usage
Product Binning
Data Analysis
Critical Path Analysis
Power Supply Noise Analysis
Substrate Noise Mitigation
Digital Design
BIOS
Drivers
Software Applications