NVIDIA’s Silicon Co-Design Group seeks a senior engineer to drive low-power validation and system bring-up for next-generation AI and accelerated computing platforms, working closely with architecture, firmware, and data infrastructure teams. This role involves defining power and performance validation strategies, building intelligent workload characterization frameworks using telemetry and AI analytics, and developing scalable automation and telemetry pipelines for silicon observability and debug workflows. The ideal candidate will have extensive experience in silicon characterization, low-power feature validation, and system integration, along with strong EE fundamentals and hands-on skills in silicon bring-up and lab validation. Proficiency in Python, data analytics, and automation framework development is essential, as well as familiarity with AI/ML technologies for telemetry analytics and debug automation. This position offers the opportunity to influence power efficiency and production readiness of NVIDIA’s globally shipped products.
Skills
Python
AI/ML
LLM
Terraform
Kubernetes
Docker
CI/CD
Prometheus
Grafana
PostgreSQL
AWS
Azure
Git
Jenkins
Ansible
PowerShell
Linux
Windows
What you'll do
Define power and performance validation strategies including power targets and low-power feature methodologies.
Build intelligent workload characterization frameworks using telemetry, clustering, and AI for early issue detection.
Develop instrumentation and telemetry pipelines to support scalable silicon observability and automated validation.
Validate system-level low-power features across pre-silicon and post-silicon environments with sophisticated automation.
Create AI/ML infrastructure for telemetry analysis, anomaly detection, predictive analytics, and automated triage.
What we're looking for
10+ years experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization.
Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, and system-level validation methodologies.
Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows for silicon validation and debug.
Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation.
Familiarity with platform power management technologies such as S0ix, ASPM, RTD3, Memory Self Refresh, and system-level power-state coordination.
Strong Python, data analytics, and automation framework development skills.
Market check
Salary context
This
$168,000–$264,500
range sits above
82%
of similar postings on FindRole.
Peer median band
$140,000–$218,500
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$152,531–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.*
* 240 is the maximum number of comparable postings sampled.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
801 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 797 roles with salary data.
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Substrate Noise Mitigation
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