Senior Design Verification Engineer - GPU Memory Subsystem
Nvidia
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How this pay compares to similar roles
This role pays less than 85% of similar roles. Most pay $177,250–$235,750 — the shaded band above. At the midpoint, this role pays about $167k versus about $206k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 745 open roles on FindRole.
Listed pay typically runs $154,000–$231,000 across 423 roles with salary data.
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At a glance
As a Senior Digital ASIC Design Engineer at Qualcomm CDMA Technologies, you will join the Digital ASIC design team to develop cutting-edge hardware and software products for advanced mobile devices. Your responsibilities include creating verification plans, developing testbench environments using System Verilog and UVM, and ensuring high-quality designs through regression testing and coverage metric closure. You will work closely with architecture and design teams to integrate third-party VIPs and support SoC DV integration verification, chip bring-up, and post-silicon debug. Essential skills include 2+ years of experience in constrained random verification, testbench development, and power-aware verification using UPF. Preferred qualifications are an MS degree in Electrical Engineering, formal verification expertise, and knowledge of GPU/CPU/DDR/Bus systems, along with Python scripting proficiency.
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