Senior GPU Design Verification Engineer - Power

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$133,600–$200,400 / yr
Posted
61 days ago
Closes
Oct 13, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $206k
This role $167k
$121k most similar roles pay here $254k

This role pays less than 85% of similar roles. Most pay $177,250–$235,750 — the shaded band above. At the midpoint, this role pays about $167k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 745 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 423 roles with salary data.

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At a glance

TL;DR · Senior GPU Design Verification Engineer - Power

As a Senior Digital ASIC Design Engineer at Qualcomm CDMA Technologies, you will join the Digital ASIC design team to develop cutting-edge hardware and software products for advanced mobile devices. Your responsibilities include creating verification plans, developing testbench environments using System Verilog and UVM, and ensuring high-quality designs through regression testing and coverage metric closure. You will work closely with architecture and design teams to integrate third-party VIPs and support SoC DV integration verification, chip bring-up, and post-silicon debug. Essential skills include 2+ years of experience in constrained random verification, testbench development, and power-aware verification using UPF. Preferred qualifications are an MS degree in Electrical Engineering, formal verification expertise, and knowledge of GPU/CPU/DDR/Bus systems, along with Python scripting proficiency.

What you'll do

  • Develop test plans and verification components for low power design features.
  • Create constraint random verification environments using System Verilog and UVM.
  • Regress designs to close required Low Power coverage metrics.
  • Integrate third-party VIPs/UVCs into the verification environment as needed.
  • Perform hardware/software co-debugging during failure analysis.
  • Support SoC DV for integration verification, chip bring-up, and post-silicon debug.

What we're looking for

  • 2+ years of hands-on experience in System Verilog and UVM-based constrained random verification.
  • 2+ years of experience in developing verification components/UVCs and testbench for RTL verification.
  • 2+ years of expertise in UPF based Power Aware verification and functional coverage model development.
  • Experience in design validation, post-silicon debug, and failure debug involving hardware software co-debug.
  • Knowledge of GPU/CPU/DDR/Bus and scripting skills using Python preferred.

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