Senior Digital Mixed-Signal (DMS) Verification Engineer

Broadcom

Quick summary

Work type: On-site
Location: Mendota Heights, MN · Broomfield, CO
Salary: $108,000–$172,800 / yr
Posted: 50 days ago
Closes: Oct 14, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k

This role $140k

$95k most similar roles pay here $232k

This role pays less than 85% of similar roles. Most pay $161,391–$215,312 — the shaded band above. At the midpoint, this role pays about $140k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Senior Digital Mixed-Signal (DMS) Verification Engineer

Apply Now Log in to save

As a Senior DMS Verification Engineer at Broadcom’s Mixed-Signal ASIC division, you will lead verification methodology initiatives and act as a technical bridge between US and Asia design centers. Your responsibilities include architecting advanced UVM-based testbenches, integrating new methodologies like SVA to enhance verification quality, and automating workflows with AI assistance to improve efficiency. You will also manage global team coordination for major tape-out projects, ensuring functional coverage closure at both block and system levels. Ideal candidates have 5+ years of experience in mixed-signal ASIC verification, deep expertise in UVM/OVM frameworks, and proficiency in SystemVerilog Assertions. Strong scripting skills are desired to automate verification processes and streamline simulation infrastructure. This role offers the opportunity to work on cutting-edge enterprise storage solutions at a Fortune 500 company.

Skills

SystemVerilog UVM OVM SystemVerilog Assertions (SVA) Python Perl Make TapeOut CI/CD Git SVK Mendota Heights MN Broomfield CO

What you'll do

Architect and maintain advanced UVM-based testbenches for complex mixed-signal ASIC products.
Champion verification quality by integrating new methodologies like SVA and UVM/OVM.
Lead initiatives to explore and integrate AI-assisted verification workflows for automation.
Own verification efforts at block and system levels for major tape-out projects.
Act as primary liaison between local US digital design teams and worldwide verification teams.

What we're looking for

5+ years of hands-on experience in digital verification of mixed-signal ASICs or SoCs.
Deep expertise in coverage-driven verification processes using UVM/OVM frameworks.
Strong understanding of event-driven simulator-based modeling techniques at the analog/digital boundary.
Proven ability to coordinate technical problem-solving across cross-site and global teams.
Hands-on experience with SystemVerilog Assertions (SVA) and behavioral modeling of analog circuits.

Save