Design Verification Engineer II | Microsoft Careers

Microsoft

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $102,100–$202,200 / yr
Posted: 9 days ago
Closes: Nov 23, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $174k

This role $152k

$90k most similar roles pay here $215k

This role pays less than 55% of similar roles. Most pay $145,000–$202,675 — the shaded band above. At the midpoint, this role pays about $152k versus about $174k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 728 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 664 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer II | Microsoft Careers

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The Design Verification Engineer position within Microsoft’s Compute Silicon and Manufacturing Engineering (CSME) team involves contributing to the verification of moderately complex system-on-chip flows, developing verification agents, environments, and testbenches, and supporting verification throughout the product lifecycle. This role requires expertise in UVM/SV for agent and testbench development, proficiency in C/C++, and experience with CPU architecture or PCIe protocol and controller/PHY. The ideal candidate will have a Master’s Degree plus 1 year of relevant experience or a Bachelor’s Degree plus 2 years, along with strong communication skills to collaborate effectively on diverse teams. This role is integral to improving planning processes, quality, delivery, scale, and sustainability in Microsoft's cloud hardware manufacturing operations.

Skills

UVM SystemVerilog C++ CPU_architecture PCIe_protocol I/O_Virtualization

What you'll do

Contributes to verification of moderately complex flows at the system on chip (SoC).
Develops verification agents, environments, and testbenches.
Supports verification through the full product life cycle from definition to silicon.
Writes test plans, develops tests, debugs failures, and works towards coverage signoff.
Improves verification methodologies, processes, and tools.

What we're looking for

Master's degree in relevant field and 1+ year of technical engineering experience required.
Bachelor's degree in relevant field and 2+ years of technical engineering experience required.
Experience developing verification agents and testbenches using UVM/SV preferred.
Proficiency with C/C++ programming languages is desired.
Knowledge in CPU architecture, PCIe protocol, or I/O Virtualization beneficial.

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