Samsung Semiconductor

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Work type: On-site
Location: San Jose, CA
Posted: 14 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $191k

$141k most similar roles pay here $252k

This listing doesn't post a salary. Most similar roles pay $165,450–$216,250.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 62 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 49 roles with salary data.

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At a glance

TL;DR · Samsung Semiconductor

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Join our dynamic team as a Staff Engineer specializing in SRAM Layout, where you will lead the development and execution of full-custom SRAM memory layout and verification flows. You’ll collaborate closely with circuit designers to translate schematics into efficient physical layouts, manage floor planning, placement, routing, and tape-out processes, and optimize designs for area, speed, power, yield, and manufacturability. Utilizing industry-standard EDA tools like Cadence Virtuoso and physical verification software, you will perform rigorous DRC/LVS checks and develop automation scripts in Perl, Tcl, or SKILL to enhance productivity. This role requires extensive experience with advanced process nodes and a strong background in SRAM layout design, coupled with leadership skills to mentor junior engineers and drive best practices within global cross-functional teams.

Skills

Candence_Virtuoso Perl Tcl SKILL DRC LVS ERC RC_Extraction Parasitic_Analysis Signal_Integrity_Verification EDA_Tools Custom_IC_Design Physical_Verification_Pods Project_Management Cross_Functional_Collaboration

What you'll do

Lead the development and execution of full-custom SRAM memory layout flows.
Translate schematics into efficient, high-performance physical layouts for SRAMs.
Design and optimize SRAM layouts at cell, array, and peripheral levels for various metrics.
Perform and close all physical verification tasks including DRC, LVS, ERC checks.
Develop automation scripts to improve productivity in SRAM layout design.

What we're looking for

Extensive experience in SRAM layout design at advanced process nodes.
Bachelor's degree with 10+ years of experience or master's with 8+ years.
Demonstrated ability to lead and mentor a team of layout engineers.
Strong proficiency with industry-standard EDA tools for custom/analog layout.
Experience in high-speed, low-power SRAM design in leading-edge nodes.
Scripting/automation skills (Perl, Tcl, SKILL) to improve productivity.

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