RTL Power Optimization Engineer

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $116,000–$189,750 / yr
Posted: 52 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $184k

This role $153k

$104k most similar roles pay here $227k

This role pays less than 73% of similar roles. Most pay $152,875–$214,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · RTL Power Optimization Engineer

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The RTL Power Optimization Engineer – New College Grad 2026 joins a team focused on power optimization for data center, gaming, automotive GPU chips, and networking chips. This role involves collaborating with architects, performance engineers, software engineers, ASIC design engineers, and physical design teams to study and implement power analysis and reduction techniques. You will use internal tools and industry standard pre-silicon gate-level and RTL power analysis tools like PowerArtist or PrimeTime PX to improve product efficiency. Key responsibilities include performing comparative power analysis, identifying bugs, prototyping architectural features in Verilog, and developing AI-based optimization solutions. Required skills include proficiency in Python for automation, knowledge of VLSI concepts, and experience with low-power design patterns such as clock gating and operand isolation. You will apply machine learning techniques to solve silicon power problems across various graphics and artificial intelligence workloads.

Skills

RTL Verilog Python Machine Learning Artificial Intelligence Power Analysis VLSI Logic Synthesis place‑and‑route PowerArtist PrimeTime PX Digital Design

What you'll do

Use internal and industry-standard tools to perform pre-silicon gate-level and RTL power analysis.
Develop and implement AI-based solutions for RTL and architectural power optimization.
Identify power bugs and trends by performing comparative power analysis across various workloads.
Collaborate with architects and designers to interpret power data and drive necessary design fixes.
Create and share best practices for pre-silicon power analysis methodologies.
Prototype new architectural features in Verilog and analyze their associated power consumption.
Build automation scripts and data pipelines using Python for AI/ML-driven power optimization flows.

What we're looking for

Pursue or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, or related fields.
Experience or coursework in AI, Digital Design, and VLSI concepts is required.
Knowledge of RTL power optimization fundamentals including switching activity and low-power design patterns.
Understanding of backend flows such as logic synthesis and place-and-route impacts on post-layout power and timing.
Familiarity with RTL implementation of low-power techniques like clock gating, operand isolation, and power gating.
Experience using industry power analysis tools such as PowerArtist or PrimeTime PX.
Strong Python programming skills for building automation scripts and AI/ML-driven analysis flows.
Hands-on experience in Machine Learning and Artificial Intelligence to solve EDA and silicon power problems.

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