RTL Power Optimization Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $116,000–$189,750 / yr
Employment: Full-time
Posted: 98 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $153k

$103k $241k

below market most similar roles pay here above market

This role pays less than 76% of similar roles. Most pay $154,802–$223,000 — the blue band above. At the midpoint, this role pays about $153k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · RTL Power Optimization Engineer

Role Posting Log in to save

The RTL Power Optimization Engineer – New College Grad 2026 joins the team responsible for power optimization of data center, gaming, automotive GPU chips, and networking chips. This role involves providing architecture, micro-architecture, RTL design, and AI-based power optimization solutions. You will collaborate with various engineering teams to study and implement power analysis and reduction techniques for next-generation products. Daily tasks include using internal and industry-standard pre-silicon gate-level and RTL power analysis tools, developing best practices, and performing comparative power analysis to identify trends or anomalies. You will prototype architectural features in Verilog, use Python for automation and AI/ML-driven analysis flows, and apply low-power techniques like clock gating and operand isolation. The work focuses on gaining early insights into energy consumption for graphics and artificial intelligence workloads.

Skills

RTL Design Verilog Power Analysis Machine Learning Artificial Intelligence Python VLSI Logic Synthesis place‑and‑route PowerArtist PrimeTime PX Clock Gating Power Gating Digital Design Data Pipelines

What you'll do

Use internal and industry-standard tools to perform pre-silicon gate-level and RTL power analysis.
Develop and implement RTL and architectural power optimization solutions using artificial intelligence.
Identify power bugs and anomalies by interpreting data and driving design teams to implement fixes.
Select and run diverse workloads to analyze energy consumption for graphics and AI applications.
Prototype new architectural features in Verilog and conduct subsequent power analysis.
Develop and share best practices for performing pre-silicon power analysis across the organization.
Build automation scripts and data pipelines using Python for AI/ML-driven power optimization flows.

What we're looking for

Pursue or recently complete a MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
Possess coursework or experience in AI, Digital Design, and VLSI concepts.
Understand RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and low-power design patterns.
Know backend flows such as logic synthesis and place-and-route and their impact on post-layout power and timing.
Be familiar with RTL implementation of low-power techniques like clock gating, operand isolation, and power gating strategies.
Have exposure to industry power analysis tools such as PowerArtist or PrimeTime PX.
Possess strong Python programming skills for building automation scripts and AI/ML-driven analysis flows.
Have hands-on experience in Machine Learning and Artificial Intelligence to apply ML techniques to EDA and silicon power problems.

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