RFIC Layout Engineer

What you'll do

• Perform detailed transistor-level layout of RF and analog circuit blocks including LNAs, mixers, PLLs, and power amplifiers.
• Execute block-level and top-level floorplanning in coordination with circuit designers.
• Conduct layout reviews for power/ground routing, electromigration, signal path checks, and differential matching.
• Manage the full verification flow including extraction, DRC, LVS, and DFM checking.
• Perform top-level layout integration and manage associated project schedules.
• Implement advanced layout techniques to minimize parasitics, provide RF shielding, and optimize high-frequency routing.
• Identify failure-prone circuit structures and collaborate with designers to resolve potential issues.
• Lead other layout engineers during the top-level integration process.

What we're looking for

• Minimum of 8 years of related experience required.
• Good understanding of RC delay, electromigration, and coupling.
• Ability to identify failure-prone circuit/layout structures and collaborate with designers to resolve issues.
• Excellent communication skills and ability to work with multi-functional teams.
• Knowledge of layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing (preferred).
• Experience in custom RF/analog layout for radio transceivers with deep sub-micron CMOS knowledge including FinFET (preferred).
• Understanding of guard rings, DNW, PN junctions, and sophisticated process effects like LOD and WPE (preferred).
• Proficiency in CALIBRE tools, CADENCE layout tools, or scripting in PERL/SKILL (preferred).