RFIC Layout Engineer

The RFIC Layout Engineer joins the wireless SOC organization to develop high-performance, energy-efficient wireless silicon. This role involves performing detailed transistor-level layout for various RF and analog circuit blocks, including LNAs, mixers, PLLs, modulators, power amplifiers, and baseband filters. The engineer is responsible for block-level and top-level floorplanning, as well as managing the full verification flow involving extraction, DRC, LVS, and DFM checking. Key tasks include reviewing power/ground routing, electromigration, signal path checks, and differential matching while ensuring proper RF shielding and high-frequency routing. The position requires expertise in deep sub-micron CMOS FinFET technology, proficiency with CADENCE layout tools, and knowledge of process effects like LOD and WPE. Candidates should possess strong skills in identifying failure-prone structures and collaborating with multi-functional teams to resolve complex integration challenges within the wireless system domain.