Principal System Performance Telemetry Architect

Arm Holdings

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TXSan Jose, CASan Diego, CAWaltham, MARaleigh, NCSeattle, WA
Salary
$249,900–$338,100 / yr
Posted
13 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $215k
This role $294k
$147k $359k
below market most similar roles pay here above market

This role pays more than 92% of similar roles. Most pay $174,900–$255,250 — the blue band above. At the midpoint, this role pays about $294k versus about $215k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 113 open roles on FindRole.

Listed pay typically runs $208,450–$282,050 across 112 roles with salary data.

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At a glance

TL;DR · Principal System Performance Telemetry Architect

The Principal System Performance Telemetry Architect joins the Central Technology Group's system architecture team to shape performance telemetry and profiling for AI infrastructure, edge platforms, and physical AI systems. You will architect how performance data is captured, correlated, and exposed across complex SoCs, including CPUs, accelerators, memory, interconnects, and multi-die systems. Responsibilities include defining hardware counters, events, metrics, and traces, while driving specifications for workload characterization and bottleneck identification. You will collaborate with SoC architects and software teams to translate debug needs into hardware requirements. Required skills include experience with heterogeneous SoC architectures, performance modeling, and tools like NVIDIA Nsight, Intel VTune, Linux perf, Arm Streamline, and Arm Performance Studio. This role solves critical hardware-software observability problems for cloud, edge, and physical AI platforms.

What you'll do

  • Define system-level performance telemetry architecture for hardware counters, events, metrics, and traces across SoCs.
  • Drive architecture specifications for workload characterization and bottleneck identification on cloud, edge, and AI platforms.
  • Architect mechanisms to collect and correlate performance telemetry across hardware-software layers for debugging.
  • Translate performance and debug requirements into specific hardware telemetry specifications for SoC architects.
  • Provide architectural guidance to software and firmware teams to enable effective use of hardware telemetry.
  • Support silicon bring-up, performance validation, and debug activities across multidisciplinary teams.

What we're looking for

  • Relevant experience in system architecture, performance engineering, performance analysis, profiling, or performance modeling for complex compute platforms.
  • Strong understanding of heterogeneous SoC architectures, including CPUs, accelerators, memory systems, interconnects, I/O, and multi-die systems.
  • Experience with hardware performance counters, events, traces, profiling infrastructure, or system-level observability.
  • Hands-on experience with profiling tools such as NVIDIA Nsight, Intel VTune, Linux perf, Arm Streamline, Arm Performance Studio, or equivalent tools.
  • Strong understanding of performance analysis methodologies, including workload characterization, bottleneck identification, latency and bandwidth analysis, and power-performance optimization.
  • Understanding of how hardware telemetry is exposed and consumed across firmware, operating systems, virtualization layers, runtimes, and developer tools.
  • Experience collaborating with cross-functional teams with strong communication and technical leadership skills.
  • Experience with silicon bring-up, performance validation, debug, or hardware-software performance correlation (preferred).

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