Principal Silicon Engineer - Networking | Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$139,900–$274,800 / yr
Posted
9 days ago
Closes
Dec 2, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k
This role $207k
$124k most similar roles pay here $291k

This role pays more than 58% of similar roles. Most pay $158,925–$216,300 — the shaded band above. At the midpoint, this role pays about $207k versus about $188k for comparable roles.

Based on 238 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 1568 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 1397 roles with salary data.

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TL;DR · Principal Silicon Engineer - Networking | Microsoft Careers

The Data Processing Unit (DPU) team within Azure Hardware Systems & Infrastructure group seeks a Principal Silicon Engineer to lead front-end micro-architecture and RTL implementation for high-performance networking accelerator modules. This role involves collaborating closely with the software team on programmable design strategies, verification, and modeling while addressing complex datacenter challenges. Ideal candidates will have extensive experience in SoC definition and development, deep knowledge of Ethernet, RDMA, TCP/IP, MAC/PCS, packet forwarding, P4 pipelines, and networking blocks, along with proficiency in Verilog, System Verilog, UVM, C++, Python, and Perl. The position requires expertise in low power microarchitecture techniques and complex subsystem verification, offering a unique opportunity to work on planet-scale silicon solutions that drive innovation in datacenter infrastructure.

What you'll do

  • Develop front-end micro-architecture for networking accelerator modules.
  • Implement RTL design for high-performance, low-power DPU silicon.
  • Collaborate with software team on programmable design strategies.
  • Verify complex subsystems involving multiple design modules.
  • Utilize Verilog, System Verilog, and UVM for verification tasks.

What we're looking for

  • BS/MS in Electrical Engineering or equivalent degree
  • 15+ years of design verification and architecture experience
  • Expertise in Ethernet, RDMA, TCP/IP, MAC/PCS, packet forwarding, P4 pipelines
  • Deep understanding of complex SoC definition and development
  • Experience with low power microarchitecture techniques and Verilog/System Verilog
  • Proficiency in UVM, C++, Python, Perl for verification and modeling
  • Hands-on experience with VSCODE or Cursor IDEs and AI agents

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