Hardware Applications Engineer
Qualcomm
At a glance
AI generatedAs a Senior Low Power Design Engineer on Qualcomm Atheros' Integrated Wireless Technology team, you will develop technical specifications and deliver detailed low-power micro-architecture designs for WiFi technology and SOC design. Your day-to-day responsibilities include working closely with the verification team to create verification plans and participating in debug phases throughout the full ASIC development process from RTL implementation through post-silicon bring-up. You will also conduct silicon power measurements, correlate power data, and use ARM IPs for full chip debug. Essential skills include experience in SoC low-power micro-architecture, Power Intent/Implementation, power optimization, and analysis tools. Preferred qualifications involve expertise with ARM IP-based full chip debug, PCIE/USB peripherals, CPU subsystem design, and multi-domain clocking protocols like AHB, APB, and AXI.
Skills
What you'll do
What we're looking for
Market check
This $176,300–$264,500 range sits above 87% of similar postings on FindRole.
Peer median band
$136,000–$218,500
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$142,450–$203,300
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 569 open roles on FindRole.
Listed pay typically runs $148,300–$224,400 across 536 roles with salary data.
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