Principal AI Silicon Architect

Microsoft

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$165,600–$296,400 / yr
Posted
12 days ago
Freshness
Confirmed live yesterday
Closes
Apr 13, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $236k
This role $231k
$150k $312k
below market most similar roles pay here above market

This role pays less than 52% of similar roles. Most pay $196,750–$275,087 — the blue band above. At the midpoint, this role pays about $231k versus about $236k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

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At a glance

TL;DR · Principal AI Silicon Architect

The Principal AI Silicon Architect joins the AI Silicon Architecture team within the Cloud Hardware, and Infrastructure Engineering group. This role involves owning the end-to-end power architecture for high-power AI accelerator SoCs, encompassing the SoC, package, board, and system levels. Key responsibilities include defining power-management architectures, including DVFS, clock and power gating, and workload-aware power management. The architect must manage high-power operating conditions, transient behavior, and thermal constraints while translating product requirements into silicon-level power budgets. The role requires deep expertise in power integrity, voltage droop, and power delivery network design for high-performance datacenter-class silicon like GPUs or HPC processors. Candidates must navigate complex tradeoffs between performance, power, reliability, cost, and implementation complexity across multi-die or chiplet architectures to optimize system-level efficiency.

What you'll do

  • Own the end-to-end power architecture for high-power AI accelerator SoCs across the SoC, package, board, and system.
  • Define SoC and package-level power-management architectures including DVFS, clock gating, and workload-aware power management.
  • Design architectures for high-power operating conditions to manage workload power excursions, peak power, and thermal constraints.
  • Translate workload and product requirements into system-level power budgets, design targets, and architectural requirements.
  • Define SoC-to-system interfaces and control mechanisms for power, thermal, and platform management.
  • Drive architectural tradeoffs across performance, power, thermal limits, reliability, area, cost, and implementation complexity.
  • Provide technical leadership through the development lifecycle including architecture specification, design reviews, and silicon bring-up.

What we're looking for

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of technical engineering experience.
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 10+ years of technical engineering experience.
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 12+ years of technical engineering experience.
  • Ability to meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check.
  • Must provide proof of citizenship, US residency, or other protected status for export control regulations.
  • Significant industry experience in SoC power architecture, power delivery, or power management for high-performance SoCs (preferred).
  • Demonstrated experience architecting and optimizing power delivery across silicon, package, board, and power supply levels (preferred).
  • Experience with AI accelerators, GPUs, HPC processors, or other high-power datacenter-class silicon (preferred).

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