Low Power Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$175,000–$308,500 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $242k
$124k $328k
below market most similar roles pay here above market

This role pays more than 81% of similar roles. Most pay $162,000–$241,750 — the blue band above. At the midpoint, this role pays about $242k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Low Power Design Engineer

Role Posting Log in to save

JOB TITLE: Low Power Design Engineer The Low Power Design Engineer joins the wireless silicon development team within the wireless SOC organization. This role focuses on designing power management logic for complex wireless communication SoCs to ensure high energy efficiency. Key responsibilities include defining SoC power management features to meet product requirements, implementing logic, and collaborating with XF teams for verification. The engineer will also support power analysis, post-silicon correlation, and bring-up debug efforts. Required technical skills include proficiency in Verilog and scripting languages like Shell, Perl, or Python. Candidates must demonstrate knowledge of ASIC low power design techniques, including CDC, RDC, STA, and UPF. Experience with common SOC components such as CPUs, fabric, and peripherals is essential for solving complex power and clock management problems in wireless silicon.

Skills

Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic Power Analysis System Architecture

What you'll do

  • Define SoC power management features to meet specific product requirements.
  • Implement power management logic for complex wireless communication SoCs.
  • Verify power management logic in coordination with XF teams.
  • Perform power analysis and post-silicon correlation efforts for the Power team.
  • Provide post-silicon bring up and debug support.
  • Apply ASIC low power design techniques to SoC components.

What we're looking for

  • BS degree and a minimum of 10 years of relevant industry experience.
  • Proven track record in power, clock, and reset management logic design.
  • Proficiency in Verilog language.
  • Experience in power management logic verification and debug.
  • Understanding of ASIC low power design techniques.
  • Knowledge of CDC, RDC, STA, and UPF.
  • Proficiency in scripting languages such as Shell, Perl, or Python.
  • Knowledge and experience with common SOC components like CPU, fabric, and peripherals.

Related searches

More Low Power Design Engineer jobs Low Power Design Engineer jobs in San Diego All jobs at Apple Inc

More like this

Similar roles

Low Power Design Engineer

Apple Inc

Irvine, CA 2 days ago $175,000–$308,500
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
10+ yrs exp
Save

Low Power Design Engineer

Apple Inc

San Diego, CA 2 days ago $122,700–$214,300
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
Save

Low Power Design Engineer

Apple Inc

Sunnyvale, CA 2 days ago $184,700–$324,800
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic Power Analysis System Architecture
10+ yrs exp
Save

Low Power Design Engineer

Apple Inc

Irvine, CA 2 days ago $122,700–$214,300
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
Save

Low Power Design Engineer

Apple Inc

Sunnyvale, CA 2 days ago $129,300–$225,300
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
Save

SoC Power Design Engineer

Qualcomm

San Diego, CA 10 days ago $121,800–$182,600
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting
2+ yrs exp
Save