Low Power Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $122,700–$214,300 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k

This role $168k

$108k $256k

below market most similar roles pay here above market

This role pays less than 67% of similar roles. Most pay $162,000–$241,750 — the blue band above. At the midpoint, this role pays about $168k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · Low Power Design Engineer

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The Low Power Design Engineer joins the wireless silicon development team to focus on highly energy efficient and low power design for wireless communication SoCs. The role involves defining SoC power management features to meet product requirements and implementing the corresponding power management logic. Key responsibilities include working with XF teams to verify logic, supporting power analysis and post-silicon correlation efforts, and providing post-silicon bring up and debug support. Candidates must demonstrate proficiency in Verilog and scripting languages like Shell, Perl, or Python. Required technical knowledge includes ASIC low power design techniques, CDC, RDC, STA, and UPF. The position requires experience with common SOC components such as CPUs, fabric, and peripherals to solve complex power management challenges within the wireless silicon product area.

Skills

Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis

What you'll do

Define SoC power management features to meet specific product requirements.
Implement power management logic for complex wireless communication SoCs.
Verify power management logic in coordination with XF teams.
Perform power analysis and post-silicon correlation efforts for the Power team.
Provide post-silicon bring-up and debug support.
Apply ASIC low power design techniques to SoC components.

What we're looking for

Minimum requirement of a bachelor's degree.
Proven track record in power, clock, and reset management logic design.
Proficiency in Verilog language.
Experience in power management logic verification and debug.
Understanding of ASIC low power design techniques.
Knowledge of CDC, RDC, STA, and UPF.
Proficiency in scripting languages such as Shell, Perl, or Python.
Knowledge and experience with common SoC components like CPU, fabric, and peripherals.
SoC level power management logic experience (preferred).
SoC top level integration experience (preferred).
System architecture knowledge (preferred).
Post-silicon functional debug and power correlation experience (preferred).

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