Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Low Power Design Engineer Remove filter Clear all

7 of up to 20 (filtered)

Low Power Design Engineer

Apple Inc

Sunnyvale, CA 2 days ago $129,300–$225,300
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
Save

Low Power Design Engineer

Apple Inc

San Diego, CA 2 days ago $122,700–$214,300
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
Save

Low Power Design Engineer

Apple Inc

Irvine, CA 2 days ago $122,700–$214,300
Actively hiring Confirmed live yesterday Posted this week High trust Below market
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
Save

Low Power Design Engineer

Apple Inc

Sunnyvale, CA 2 days ago $184,700–$324,800
Actively hiring Confirmed live today Posted this week High trust Above market
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic Power Analysis System Architecture
10+ yrs exp
Save

Low Power Design Engineer

Apple Inc

San Diego, CA 2 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic Power Analysis System Architecture
10+ yrs exp
Save

Low Power Design Engineer

Apple Inc

Irvine, CA 2 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
10+ yrs exp
Save

Design Engineer (Low Power)

Qualcomm

Santa Clara, CA 43 days ago $190,200–$285,400
Actively hiring Confirmed live yesterday High trust Above market
ASIC Design Low Power Design RTL Synthesis Timing Closure ARM IP AMBA AHB APB AXI PCIe USB silicon bring up Power Analysis Emulation SoC micro architecture 802.11x Multi-domain Clocking
7+ yrs exp
Save