CPU DFT Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $129,300–$194,700 / yr
Posted: 40 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k

This role $162k

$115k $262k

below market most similar roles pay here above market

This role pays less than 78% of similar roles. Most pay $173,450–$227,300 — the blue band above. At the midpoint, this role pays about $162k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · CPU DFT Verification Engineer

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The CPU DFT Verification Engineer joins the processor verification team to ensure the functional correctness of DFT logic within a chip design effort. The role involves collaborating with architecture, RTL, and DFT designers to execute test plans, develop testbenches, and debug simulation failures. Key responsibilities include developing coverage monitors, creating Verilog checkers or assertions, and working with the silicon bringup team to develop necessary tests. Candidates should possess academic experience in computer architecture and digital design using Verilog. Preferred skills include knowledge of JTAG, MBIST, and scan methodologies, as well as proficiency in Python, Perl, or TCL. The position requires a deep understanding of digital logic design, DFT architecture, and verification methodologies to solve complex design issues during the verification of CPU blocks.

Skills

DFT Verilog System-Verilog Python Perl TCL JTAG MBIST Scan RTL Digital Logic Design Computer Architecture Assertions Simulation Silicon Bringup

What you'll do

Verify the functional correctness of DFT logic with architecture, RTL, and DFT designers.
Execute comprehensive test plans for DFT logic.
Develop testbenches and specific tests according to established test plans.
Debug simulation failures to ensure design integrity.
Develop coverage monitors and analyze results to ensure all test cases are covered.
Develop Verilog checkers or assertions to verify the design.
Develop tests to support the silicon bringup effort with the silicon bringup team.

What we're looking for

Minimum BS degree.
Academic experience in computer architecture.
Academic experience in digital design using Verilog.
Master’s degree (preferred).
Knowledge of DFT and structural debug concepts and methodologies including JTAG, MBIST, and scan (preferred).
Knowledge of digital logic design, debug features, and DFT architecture and microarchitecture (preferred).
Proficiency in programming and scripting in Python, Perl, or TCL (preferred).
Experience or academic knowledge in design verification methodology, including testplans, Verilog/System-Verilog testbenches, transactors, and checkers (preferred).

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