HSIO Validation Lead, Silicon Co-Design

What you'll do

• Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces.
• Drive root cause analysis across protocol behavior, signal integrity, firmware, driver interactions, and silicon marginalities.
• Define validation strategies including test coverage, debug priorities, margining methodology, and stress criteria.
• Build and manage AI agents for automated debug triage, intelligent data pipelines, and analysis flows.
• Ensure robust interoperability across retimers, switches, accelerators, CPUs, GPUs, and multi-device system topologies.
• Translate silicon findings into methodology and coverage improvements for future product generations.
• Provide technical analysis to drive alignment across architecture, logic design, circuit design, and product teams.

What we're looking for

• BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent lab experience.
• 8+ years of experience in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.
• Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interface technologies.
• Strong signal integrity fundamentals including SERDES behavior, link training, equalization, clocking, and power management.
• Hands-on experience with oscilloscopes, BERTs, protocol analyzers, logic analyzers, and silicon debug tools.
• Ability to debug across the full stack including hardware, firmware, drivers, and platform design.
• Recognized depth in PCIe, NVLink, CXL, or advanced SERDES validation with complex failure resolution (preferred).
• Experience building AI-driven flows for HSIO debug or failure triage (preferred).