HSIO Validation Lead

Nvidia

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
17 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k
This role $216k
$141k most similar roles pay here $278k

This role pays more than 70% of similar roles. Most pay $172,000–$227,300 — the shaded band above. At the midpoint, this role pays about $216k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · HSIO Validation Lead

As the HSIO Validation Lead – Silicon Co-Design, you will join the Silicon Co-Design Group to manage the critical boundary between design and production for high-speed interfaces. You will own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across GPUs, CPUs, and SoCs. Your daily work involves resolving complex failures by analyzing protocol behavior, signal integrity, firmware, driver interactions, and silicon marginalities. You will define validation strategies, set test coverage, and build AI agents for automated debug triage and data pipelines. To succeed, you must possess deep expertise in PCIe, NVLink, CXL, Ethernet, or USB, alongside proficiency with oscilloscopes, BERTs, and protocol analyzers. This role solves the technical challenge of ensuring reliable high-speed data movement across complex multi-device system topologies to prevent customer escapes and ensure production readiness.

What you'll do

  • Own post-silicon bring-up, characterization, and validation of PCIe, NVLink, C2C, and other high-speed interfaces.
  • Perform root cause analysis across protocol behavior, signal integrity, firmware, and silicon marginalities to resolve complex failures.
  • Define validation strategies including test coverage, debug priorities, margining methodology, and stress criteria for new programs.
  • Develop and manage AI agents to automate debug triage, data pipelines, and analysis flows.
  • Ensure robust interoperability across retimers, switches, accelerators, CPUs, GPUs, and multi-device system topologies.
  • Translate findings from real silicon into improved methodologies and coverage for future product generations.
  • Provide technical data and analysis to drive alignment across architecture, logic design, firmware, and product teams.

What we're looking for

  • BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent lab experience.
  • 8+ years of experience in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.
  • Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar technologies.
  • Strong signal integrity fundamentals including SERDES behavior, link training, equalization, and power management.
  • Proficiency with lab equipment such as oscilloscopes, BERTs, protocol analyzers, logic analyzers, and silicon debug tools.
  • Ability to debug across the full stack of hardware, firmware, drivers, and platform design.
  • Statistical proficiency to analyze marginal distributions and identify critical data trends.
  • Experience building or deploying AI-driven flows for HSIO debug or failure triage.

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