This role pays more than
99%
of similar roles. Most pay
$174,600–$254,793
— the shaded band above.
At the midpoint, this role pays about
$404k
versus about
$215k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
896 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 876 roles with salary data.
Distinguished Engineer, End-to-End Scaling Performance Architecture will join the architecture organization to define long-term performance strategies for accelerated computing systems scaling from single processors to multi-die, multi-GPU, and multi-node platforms. The role involves identifying bottlenecks in data movement, communication, memory behavior, and topology to guide multiple product generations. You will translate AI, HPC, and accelerated computing application behaviors into architectural requirements while evaluating trade-offs across bandwidth, latency, capacity, coherence, power, area, cost, programmability, and resiliency. Key technical components include DRAM, NVLink, and chip-to-chip interconnects. Candidates must possess an MSEE, MSCE, or PhD in a related field with over 18 years of experience. You will collaborate with hardware, software, and compiler teams to align decisions around shared performance limits while mentoring architects and building technical communities to solve complex scaling challenges across the entire system stack.
Establish common workload scenarios, scaling metrics, and decision frameworks to guide architecture teams' proposals.
Identify architectural discontinuities and emerging technology opportunities to shape long-term product and technology decisions.
Align cross-functional teams on shared performance limits and high-value opportunities across silicon, systems, and software.
Mentor system performance architects and build technical communities to influence the direction of large-scale accelerated computing.
What we're looking for
Must possess an MSEE, MSCE, PhD, or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Requires 18+ years of relevant industry or academic experience.
Experience must include setting architecture direction for complex, high-performance systems.
Must have a deep understanding of system performance and scaling involving DRAM behavior, high-bandwidth fabrics like NVLink, and C2C communication.
Must possess strong application-level intuition to connect workload algorithms and data movement to architectural choices.
Experience in workload characterization, analytical or simulation-based performance modeling, and bottleneck analysis is required.
Demonstrated ability to create and advance multi-generation technical strategies through influence across silicon, systems, software, and application teams.
Ability to mentor senior engineers into leadership roles and build strong technical communities.
GPU
HPC
Deep Learning
C++
Python
Bash
Linux
Parallel Filesystems
Accelerated Computing
System Administration
Telemetry
Visualization Pipelines
I/O Stacks
HPC
CUDA
C++
C
MPI
NCCL
NVSHMEM
UCX
Infiniband
Ethernet
PyTorch
TensorFlow
GPU Architecture
Parallel Programming
Deep Learning
System Architecture
PCIe
NVLink