Distinguished Engineer, End-to-End Scaling Performance Architecture

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXRedmond, WA
Salary
$320,000–$488,750 / yr
Employment
Full-time
Posted
91 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $233k
This role $404k
$140k $526k
below market most similar roles pay here above market

This role pays more than 99% of similar roles. Most pay $195,000–$270,500 — the blue band above. At the midpoint, this role pays about $404k versus about $233k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Distinguished Engineer, End-to-End Scaling Performance Architecture

JOB TITLE: Distinguished Engineer, End-to-End Scaling Performance Architecture The Distinguished Engineer, End-to-End Scaling Performance Architecture joins the architecture organization to define how future accelerated computing systems scale from single processors to multi-die, multi-GPU, and multi-node platforms. This role involves setting long-term performance strategies across applications, systems, and architecture, specifically focusing on DRAM, NVLink, and chip-to-chip interconnects. You will identify bottlenecks in data movement, communication, memory behavior, and topology to guide multiple product generations. Key responsibilities include translating AI and HPC application behaviors into architectural requirements, evaluating trade-offs in bandwidth, latency, and power, and mentoring system performance architects. Required expertise includes MSEE, MSCE, or PhD degrees with over 18 years of experience in electrical or computer engineering, focusing on high-performance systems, workload characterization, and analytical or simulation-based performance modeling.

What you'll do

  • Define multi-generation strategies for application scaling across DRAM, NVLink, C2C, and the software stack.
  • Translate AI and HPC application behaviors into architectural requirements, performance targets, and investment priorities.
  • Analyze how bottlenecks shift as workloads scale across dies, GPUs, nodes, and communication patterns.
  • Evaluate system-level trade-offs regarding bandwidth, latency, capacity, topology, power, area, and cost.
  • Establish common workload scenarios, scaling metrics, and decision frameworks for architecture teams.
  • Identify architectural discontinuities and emerging technology opportunities to shape long-term product decisions.
  • Align diverse architecture teams around shared performance limits and high-value technical opportunities.
  • Mentor system performance architects and generate sustained intellectual property for accelerated computing.

What we're looking for

  • MSEE, MSCE, PhD, or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 18+ years of relevant industry or academic experience.
  • Experience setting architecture direction for complex, high-performance systems.
  • Deep understanding of system performance and scaling, including DRAM behavior, NVLink, and C2C communication.
  • Ability to connect workload algorithms, parallelism, communication, locality, and data movement to architecture choices.
  • Experience with workload characterization, analytical or simulation-based performance modeling, bottleneck analysis, and architecture trade-off evaluation.
  • Demonstrated ability to create and advance a multi-generation technical strategy through influence across silicon, systems, software, and application teams.
  • Experience mentoring senior engineers into broader architecture leadership roles and building strong technical communities.

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