Digital Layout Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $144,600–$263,800 / yr
Posted: 117 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $202k

This role $204k

$130k $278k

below market most similar roles pay here above market

This role pays more than 55% of similar roles. Most pay $162,559–$241,750 — the blue band above. At the midpoint, this role pays about $204k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Digital Layout Design Engineer

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The Digital Layout Design Engineer joins the Digital Design Engineering group within the microprocessor group to design state-of-the-art ASICs. This role involves creating extraordinary custom digital macros and libraries on the latest technology nodes. You will design complex custom layouts for digital circuits in deep SubMicron CMOS technologies, review floorplans with circuit designers, and run layout design verification tools. Key responsibilities include interpreting LVS, DRC, and ERC reports to resolve layout issues while negotiating tradeoffs with the circuit design team. You will utilize advanced CAD tools, including MENTOR GRAPHICS or CADENCE, and may use CSH, PERL, or SKILL scripting. The work focuses on solving physical design challenges such as RC delay, electromigration, self-heating, and cross-capacitance within a high-speed silicon design environment.

Skills

Digital Layout CMOS LVS DRC ERC Floorplanning Standard Cell Planning Hierarchical Layout Assembly CADENCE MENTOR GRAPHICS CALIBRE Perl SKILL CSH Layout Automation Memory Compiler Development

What you'll do

Design complex custom layouts for digital circuits using deep SubMicron CMOS technologies.
Review and analyze floorplans and complex circuits in coordination with circuit designers.
Run a complete set of layout design verification tools on completed megacells.
Plan and schedule work while negotiating layout tradeoffs with the circuit design team.
Interpret LVS, DRC, and ERC reports to identify the fastest paths for layout completion.
Use advanced CAD tools and mask design knowledge to perform layout corrections.
Create robust physical design representations of circuits to meet engineering specifications.

What we're looking for

Bachelor's degree in a relevant field of study.
3 years of relevant experience.
Experience in custom layout design of deep SubMicron CMOS circuits (preferred).
High level proficiency in layout floorplanning, standard cell planning, and hierarchical layout assembly (preferred).
Good understanding of RC delay, electromigration, self-heating, and cross capacitance issues (preferred).
Knowledge of MENTOR GRAPHICS or CADENCE layout tools (preferred).
Scripting skills in CSH, PERL, or SKILL (preferred).
Experience in layout automation, memory compiler development, or low power datapaths (preferred).