Digital Layout Design Engineer

What you'll do

• Design complex custom layouts for digital circuits using deep SubMicron CMOS technologies.
• Review and analyze floorplans and complex circuits in coordination with circuit designers.
• Run a complete set of layout design verification tools on completed megacells.
• Plan and schedule work while negotiating layout tradeoffs with the circuit design team.
• Interpret LVS, DRC, and ERC reports to identify the fastest paths for layout completion.
• Use advanced CAD tools and mask design knowledge to perform layout corrections.
• Create robust physical design representations of circuits to meet engineering specifications.

What we're looking for

• Bachelor's degree in a relevant field of study.
• 3 years of relevant experience.
• Experience in custom layout design of deep SubMicron CMOS circuits (preferred).
• High level proficiency in layout floorplanning, standard cell planning, and hierarchical layout assembly (preferred).
• Good understanding of RC delay, electromigration, self heating, and cross capacitance issues (preferred).
• Excellent communication skills and ability to work with multi-functional teams (preferred).
• Knowledge of MENTOR GRAPHICS or CADENCE layout tools (preferred).
• Scripting skills in CSH, PERL or SKILL; experience in layout automation; or experience in memory compiler development (preferred).