This role pays more than
84%
of similar roles. Most pay
$168,500–$230,087
— the shaded band above.
At the midpoint, this role pays about
$242k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3513 open roles
on FindRole.
Listed pay typically runs
$165,800–$277,600
across 2730 roles with salary data.
As a Design Verification Engineer, you will join the hardware team to ensure bug-free first silicon for SoC and IP designs. You will be responsible for all phases of pre-silicon verification, including establishing methodologies, developing test plans based on micro-architecture, and building scalable, portable verification environments featuring stimulus, checkers, assertions, and trackers. Your daily work involves executing verification plans, performing design bring-up, running regressions, and debugging test failures to achieve RTL freeze and tape-out. You will utilize SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL to stress designs. Additionally, you will leverage LLMs to improve execution efficiency and quality. The role focuses on the technical challenge of ensuring functional integrity for complex integrated circuits through rigorous coverage tracking and advanced verification methodologies such as power-aware UPF techniques.
What does a Design Verification Engineer earn in California?
Median $190598 from 33 postings across 7 companies.
Develop comprehensive test plans and verification methodologies based on micro-architecture specifications.
Build scalable and portable verification environments using SystemVerilog and UVM.
Create stimulus, checkers, assertions, and trackers to stress the design.
Execute and debug test failures from regression suites to ensure bug-free silicon.
Track and report verification progress using metrics such as bug counts and coverage.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform all phases of pre-silicon verification including RTL freeze and tape-out sign-off.
What we're looking for
Bachelor's degree in a technical subject area with at least 10 years of proven experience or equivalent.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, and gate level simulations (preferred).
Experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).
Experience with serial/parallel protocols (PCIe, USB, DDR), formal verification, or emulation technologies (preferred).