Careers

What you'll do

• Design and develop RTL for complex ASIC subsystems using Verilog/SV.
• Implement micro architecture and integrate designs with SoC components.
• Collaborate on low power design methodologies including UPF and CDC checks.
• Coordinate with verification, PD, DFT teams to ensure design convergence.
• Analyze tool reports and waivers from Spyglass, PrimeTime, and other EDA tools.

What we're looking for

• 5 to 8 years of experience in digital front-end design for ASICs
• Expertise in RTL coding with Verilog/VHDL/SV and familiarity with multiple clock domains
• Knowledge of UPF, power domain crossing, and low-power design methodologies
• Experience with bus protocols like AHB, AXI, SPMI, I2C, SPI
• Proficiency in formal verification tools such as Cadence LEC and Spyglass lint/CDC checks
• Understanding of full RTL to GDS flow for interaction with DFT and PD teams
• Strong documentation skills and effective communication abilities