Careers

Qualcomm

Quick summary

Work type
On-site
Location
Santa Clara, CA
Posted
103 days ago
Closes
Aug 22, 2026
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $183k
$132k most similar roles pay here $228k

This listing doesn't post a salary. Most similar roles pay $152,875–$213,093.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 270 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 196 roles with salary data.

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At a glance

TL;DR · Careers

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As a Senior Low Power Design Engineer on Qualcomm Atheros' Integrated Wireless Technology team, you will develop technical specifications and deliver detailed low-power micro-architecture designs for WiFi technology and SOC design. Your day-to-day responsibilities include working closely with the verification team to create verification plans and participating in debug phases throughout the full ASIC development process from RTL implementation through post-silicon bring-up. You will also conduct silicon power measurements, correlate power data, and use ARM IPs for full chip debug. Essential skills include experience in SoC low-power micro-architecture, Power Intent/Implementation, power optimization, and analysis tools. Preferred qualifications involve expertise with ARM IP-based full chip debug, PCIE/USB peripherals, CPU subsystem design, and multi-domain clocking protocols like AHB, APB, and AXI.

Skills

ARM SoC Design Low Power Micro-Architecture Power Intent/Implementation Power Optimization Power Estimation Silicon Debug AMBA AHB AMBA APB AXI PCIe USB RTL Implementation Verification Synthesis Timing Closure Emulation Post-Silicon Bring-Up ARM IPs

What you'll do

  • Develop technical specifications and detailed low-power micro-architecture from system requirements.
  • Implement RTL design and collaborate with verification team to create verification plans.
  • Own designs through full ASIC development process including synthesis and timing closure.
  • Conduct silicon power measurements and correlate power analysis post-silicon bring-up.
  • Debug full chip using ARM IPs and optimize for low power throughout the project lifecycle.

What we're looking for

  • 7+ years of experience in ASIC design.
  • Expertise in SoC low power micro-architecture and power optimization techniques.
  • Experience with ARM IP-based full chip debug and silicon bring up.
  • Proficiency in Power Intent/Implementation and multi-domain clocking.
  • Knowledge of AMBA bus protocols (AHB, APB) and preferred experience with AXI.

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