ASIC Packaging Signal Power Integrity Hardware Engineer

Cisco

Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$152,500–$219,200 / yr
Posted
4 days ago
Closes
Sep 25, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $186k
$133k most similar roles pay here $230k

This role pays more than 52% of similar roles. Most pay $160,000–$214,050 — the shaded band above. At the midpoint, this role pays about $186k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 186 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 186 roles with salary data.

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At a glance

TL;DR · ASIC Packaging Signal Power Integrity Hardware Engineer

Role Posting Log in to save

Join our specialized ASIC team in San Jose as a Signal and Power Integrity Engineer, where you will develop and document design rules for ultra-high-speed signaling to meet performance goals across various Cisco platforms. Your day-to-day involves analyzing signal integrity and power integrity issues, collaborating with layout teams to optimize solutions, and conducting detailed layout reviews using tools like Cadence Sigrity and Ansys HFSS. You must have expertise in high-speed design principles, SI/PI simulations, and circuit analysis with SPICE, alongside experience with advanced packaging technologies such as 2.5D ASIC integration. This role demands a deep understanding of transmission line theory and channel modeling to ensure high-quality releases for large-scale deployments.

Skills

Cadence Sigrity Ansys HFSS Keysight ADS Cadence APD Ansys EM SPICE Transmission Line Theory Electromagnetics Scattering Parameters Impedance Network Analysis 56G PAM4 SerDes Channel Modeling BER Prediction HBM UCIe CoWoS EMIB Vector Network Analysis IBIS

What you'll do

  • Develop and document design rules for ultra-high-speed signaling in ASIC packaging.
  • Analyze substrate signal integrity and power integrity to optimize solutions across interposer, substrate, and PCB.
  • Design and develop high-volume, high-quality ASIC packages including post-layout extraction and reporting.
  • Collaborate with system partners and vendors to resolve complex technical issues related to combined power and signal integrity.
  • Conduct detailed layout reviews using tools like Cadence APD and Ansys EM flows for physical design validation.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 4+ years of signal and power integrity experience.
  • Expertise in high-speed design principles including Transmission Line Theory and channel modeling.
  • Proficiency in SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
  • Experience conducting detailed layout reviews and physical design validation using Cadence APD and Ansys EM flows.
  • Working knowledge of SPICE for circuit-level analysis and performance validation.

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