ASIC Packaging Signal Integrity Engineering Technical Lead (Remote)

Cisco

Remote Actively hiring Verified listing
San Jose, CA · RTP, NC · Acton, MA · Dallas, TX · Tempe, AZ Posted 11 days ago $183,800$263,600 / year

At a glance

AI generated

TL;DR

As a Signal and Power Integrity Technical Lead at Cisco Silicon One in San Jose, CA, you will join a specialized ASIC team focused on developing cutting-edge silicon devices for complex networks. Your role involves defining and implementing design rules for ultra-high-speed signaling to meet performance goals, analyzing signal and power integrity issues, and collaborating with layout teams to optimize solutions across various platforms. You will also mentor junior engineers, lead chip architecture discussions, and ensure technical specifications are met while promoting a culture of continuous improvement. The ideal candidate has extensive experience in high-speed ASIC tape-outs, expertise in 56G PAM4 and above technologies, and hands-on skills with tools like Keysight ADS and Ansys HFSS/EM flow. Knowledge of advanced packaging techniques such as CoWoS and EMIB is preferred, along with proficiency in scripting languages like Python or MATLAB.

Skills

Keysight ADS Ansys HFSS Cadence APD SPICE Python Raptor-X MATLAB Vector Network Analysis IBIS 56G PAM4 SerDes HBM UCIe CoWoS EMIB 2.5D ASIC packaging

What you'll do

  • Develop and document design rules for ultra-high-speed signaling in ASIC packaging.
  • Analyze signal integrity and power integrity issues in substrates and provide solutions.
  • Design high-quality ASIC packages ensuring post-layout extraction and reporting accuracy.
  • Collaborate with system partners to resolve complex technical issues using advanced technology.
  • Define processes, methods, and tools for the design of complex ASIC/package developments.
  • Mentor junior engineers and support signal integrity team to meet all technical specifications.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 8+ years of signal and power integrity experience.
  • Proven track record of multiple high-speed ASIC tape-outs from a package perspective.
  • Expertise in 56G PAM4, SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics.
  • Hands-on experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
  • Deep understanding of SPICE and ability to mentor junior engineers.

Market check

Salary context

This $183,800–$263,600 range sits above 83% of similar postings on FindRole.

Peer median band

$140,000$218,850

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$152,875$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 103 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 103 roles with salary data.

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