ASIC Design Engineering Technical Lead (Hybrid)
Cisco
At a glance
AI generatedAs a Signal and Power Integrity Technical Lead at Cisco Silicon One in San Jose, CA, you will join a specialized ASIC team focused on developing cutting-edge silicon devices for complex networks. Your role involves defining and implementing design rules for ultra-high-speed signaling to meet performance goals, analyzing signal and power integrity issues, and collaborating with layout teams to optimize solutions across various platforms. You will also mentor junior engineers, lead chip architecture discussions, and ensure technical specifications are met while promoting a culture of continuous improvement. The ideal candidate has extensive experience in high-speed ASIC tape-outs, expertise in 56G PAM4 and above technologies, and hands-on skills with tools like Keysight ADS and Ansys HFSS/EM flow. Knowledge of advanced packaging techniques such as CoWoS and EMIB is preferred, along with proficiency in scripting languages like Python or MATLAB.
Skills
What you'll do
What we're looking for
Market check
This $183,800–$263,600 range sits above 83% of similar postings on FindRole.
Peer median band
$140,000–$218,850
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$152,875–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has 103 open roles on FindRole.
Listed pay typically runs $165,000–$241,400 across 103 roles with salary data.
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