Senior Custom ASIC Engineering Lead

Broadcom

Actively hiring
San Jose Innovation Drive, CA · Fort Collins, CO · Irvine Alton Parkway Bldg 1, CA Posted 16 days ago $163,800–$262,000 / year
View original post Log in to save

At a glance

AI generated

TL;DR

As a senior engineer at Broadcom’s ASIC products division, you will lead external and internal cross-functional teams in the development of advanced semiconductor chips for AI, HPC, networking, and storage. Your day-to-day responsibilities include managing customer programs from design to production, advising on EDA best practices, identifying potential risks, executing physical design flows, and collaborating with marketing, sales, legal, and regulatory compliance teams. You must have extensive experience in multiple tape-outs at advanced technology nodes, PPA tradeoffs analysis, low power design, and hands-on expertise in physical design, STA, EDA tools, and scripting languages like TCL and shell. Knowledge of DFT methods and SERDES communications protocols is beneficial. This role offers the opportunity to work on cutting-edge technologies and push the boundaries of semiconductor engineering at a global scale.

Skills

TCL Shell Scripting EDA tools Physical design STA DFT Verilog RTL coding Logic simulation Test Packaging Low power design Power management SERDES ASIC HPC Networking Storage AI

What you'll do

  • Manage external customer ASIC programs from inception to finish.
  • Advise customers on best practices in EDA flows and design methodologies.
  • Proactively assess risks to design quality and project schedule.
  • Execute physical design flows to ensure tape-out quality standards.
  • Stay updated with developments in Broadcom IPs, technology, and applications.

What we're looking for

  • Extensive experience (15+ years) in electrical engineering with a focus on ASIC development.
  • Proven track record of multiple tape-outs in advanced technology nodes.
  • Expertise in physical design, STA, EDA tools, and scripting languages like TCL and shell.
  • Deep knowledge in low power design, power management, and DFT methods.
  • Ability to lead cross-functional teams and manage customer programs from inception to production.
  • Strong analytical skills for assessing PPA tradeoffs and identifying potential risks in chip designs.

Market check

Salary context

This $163,800–$262,000 range sits above 63% of similar postings on FindRole.

Peer median band

$152,000–$228,000

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$156,875–$223,700

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 72 open roles on FindRole.

Listed pay typically runs $119,400–$192,000 across 72 roles with salary data.

Most-posted roles

View all roles at Broadcom

More like this

Similar roles

Senior ASIC Infrastructure Engineer

Nvidia

Us, Ca, Santa Clara, US 9 days ago $152,000–$241,500
Python Perl Linux CI/CD Jenkins Kubernetes Docker gitlab REST APIs webservers VCS Verdi Terraform PostgreSQL Redis Prometheus Grafana RAG MCP LangGraph Transformer RL GenAI

Senior ASIC Verification Engineer

Nvidia

Remote (Us, Ca, Santa Clara, US) 140 days ago $136,000–$218,500
SystemVerilog UVM VCS Verdi PCIe CXL Python Go Docker CI/CD
Remote

ASIC Design Engineering Technical Lead (Hybrid)

Cisco

Remote (Usa-San Jose, US) 57 days ago $183,800–$263,600
Verilog SystemVerilog RTL ASIC timing closure power optimization clock gating simulation synthesis static timing analysis
Remote

ASIC Design Verification Technical Leader

Cisco

Remote (Usa-Carlsbad, US) 49 days ago $163,600–$234,600
SystemVerilog UVM Python Perl TCL Shell SerDes D2D_PHY_IP ODSP Ethernet UCIE UAL SPI I2C Formal_Verification Verilog Veloce HAPS Emulation_Pods
Remote

ASIC Link Modeling Technical Leader

Cisco

Remote (Usa-Carlsbad, US) 45 days ago $189,300–$271,500
Python C/C++ MATLAB Keysight ADS Synopsys HSPICE Cadence IBIS-AMI Linux Perl TCL PAM4 ASIC SoC EDA SI simulation D2D PHY Ethernet SerDes DSP
Remote

ASIC Design Engineer

Qualcomm

Santa Clara, Ca,Us, US 78 days ago $126,700–$190,100
Python Perl AMBA AHB APB AXI PCIe USB CoreSight AI/ML DFT FPGA CDC Clocking_architecture NoC