Applied Research Engineer, Chip Design

Nvidia

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$192,000–$304,750 / yr
Posted
50 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k
This role $248k
$135k most similar roles pay here $323k

This role pays more than 85% of similar roles. Most pay $167,900–$218,875 — the shaded band above. At the midpoint, this role pays about $248k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Applied Research Engineer, Chip Design

As an Applied Research Engineer, Chip Design, you will join a team at the intersection of AI and ASIC design to drive applied research into real silicon production. You will apply large language models, coding agents, and agentic systems to core chip design problems including RTL generation, design and formal verification, and PPA prediction and optimization. Your daily work involves building robust data generation pipelines using synthetic data, creating meticulous evaluation methodologies, and wiring agentic AI into EDA and validation flows such as simulation, regression, and waveform analysis. You will utilize technologies like RL, RLHF/RLAIF, SFT, DPO, and infrastructure tools including Docker, Slurm, and CI/CD. The role focuses on solving technical challenges in front-end ASIC design by integrating advanced machine learning models into existing hardware development workflows to accelerate production schedules.

What you'll do

  • Apply LLMs and agentic systems to core ASIC design problems like RTL generation and verification.
  • Develop robust data generation pipelines and evaluation methodologies to move from prototypes to production.
  • Integrate coding agents into EDA and validation flows for simulation, regression, and log analysis.
  • Optimize PPA predictions and automate complex tasks to accelerate internal chip design schedules.
  • Collaborate with the Nemotron team to improve models using domain-specific ASIC data and feedback.
  • Build and maintain infrastructure including Docker, Slurm, and CI/CD pipelines for production ML systems.
  • Conduct custom model training, fine-tuning, and post-training using proprietary technical data.

What we're looking for

  • MS or PhD in Computer Science, Electrical/Computer Engineering, or a related field.
  • 8+ years of proven industry experience.
  • Domain and technical expertise in front-end ASIC design, verification, and timing.
  • Experience applying agentic AI to chip design and optimization problems from conception to production.
  • Hands-on experience building LLM-based agents or AI tooling including context engineering, tool integration, and evaluation.
  • Experience with custom model training, fine-tuning, or post-training (SFT, RLHF/DPO) on proprietary technical data.
  • Experience building and maintaining infrastructure such as Docker, Slurm, and CI/CD.
  • Excellent written and verbal communication skills to present and explain complex technical work.

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