Applied Research Engineer, Chip Design

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$192,000–$304,750 / yr
Employment
Full-time
Posted
96 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k
This role $248k
$139k $323k
below market most similar roles pay here above market

This role pays more than 80% of similar roles. Most pay $167,975–$231,150 — the blue band above. At the midpoint, this role pays about $248k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Applied Research Engineer, Chip Design

The Applied Research Engineer, Chip Design joins the team to drive applied research at the intersection of AI and ASIC design. This role involves applying large language models, coding agents, and agentic systems to core ASIC design problems including RTL generation, design and formal verification, and PPA prediction and optimization. You will build robust data generation systems, including synthetic data, and wire coding agents into EDA and validation flows for simulation, regressions, and log analysis. Key technologies include LLMs, RL, RLHF/RLAIF, post-training, and production ML systems, alongside infrastructure tools like Docker, Slurm, and CI/CD. The work focuses on improving chip design flows by integrating domain-specific data and feedback into models to accelerate ASIC team activities and move from prototype to production.

What you'll do

  • Apply LLMs, coding agents, and agentic systems to RTL generation, design verification, and PPA optimization.
  • Deliver production-ready AI tools that accelerate ASIC design schedules and reduce engineering ramp time.
  • Build robust data generation pipelines, including synthetic data, and establish meticulous evaluation methodologies.
  • Integrate coding agents into EDA and validation flows for simulation, regression, and log analysis.
  • Develop research harnesses on top of open-source foundations to move prototypes into production.
  • Partner with internal teams to improve models using domain-specific data and post-training techniques.
  • Train and fine-tune models using SFT, RLHF, and DPO over proprietary technical data.

What we're looking for

  • MS or PhD or equivalent experience in Computer Science, Electrical/Computer Engineering, or a related field.
  • 8+ years of proven industry experience.
  • Domain and technical expertise in front-end ASIC design, verification, and timing.
  • Project experience applying agentic AI to chip design and optimization problems from conception to production.
  • Hands-on experience building LLM-based agents or AI tooling involving context engineering, tool integration, orchestration, and failure analysis.
  • Experience with custom model training, fine-tuning, or post-training (SFT, RLHF/DPO) over proprietary technical data.
  • Experience building and maintaining infrastructure such as Docker, Slurm, and CI/CD.
  • Excellent written and verbal communication skills with experience presenting complex technical work.

More like this

Similar roles

Senior AI Systems Engineer, Chip Design

Nvidia

Remote (Santa Clara, CA) +1 20 days ago
Python Machine Learning Deep Learning PyTorch TensorFlow LLM VLSI Design CI/CD Version Control Software Development AI Agents
6+ yrs exp Remote

Applied AI Engineer, VLSI Design

Nvidia

Santa Clara, CA 71 days ago $136,000–$218,500
Python LLMs Machine Learning Deep Learning RAG Vector Databases Agentic Frameworks CI/CD Version Control VLSI Design CAD Flow Data Structures Algorithms Circuit Design HW Design
5+ yrs exp Hybrid

Senior Full Chip Physical Verification Engineer

SpaceX

Palo Alto, CA +3 179 days ago $175,000–$280,000
DRC LVS PERC ESD Calibre ICV Pegasus ASIC SoC Python TCL Perl Bash Makefile DFT SerDes DDR Physical Design Flow Tapeout Rule Deck Validation
5+ yrs exp

Senior Full Chip Physical Verification Engineer

SpaceX

Irvine, CA +2 151 days ago $165,000–$260,000
DRC LVS PERC ESD Calibre ICV Pegasus ASIC SoC Python TCL Perl Bash Makefile DFT SerDes DDR Physical Design Flow Tapeout Hard IP Integration
5+ yrs exp

Foundry Advanced Device Development Engineer

Intel

Hillsboro, OR 18 days ago $136,900–$193,270
Device Physics Electrical Characterization Statistical Process Control Design of Experiments Python SQL C/C++ MATLAB JMP Perl TCL Machine Learning Deep Learning Retrieval-Augmented Generation Data Mining Circuit Simulation Process Design Kit