Staff ATE Test Engineer, High-Speed I/O & Test Infrastructure

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$130,400–$195,600 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday
Closes
Sep 9, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $171k
This role $163k
$122k most similar roles pay here $213k

This role pays more than 51% of similar roles. Most pay $137,325–$204,200 — the shaded band above. At the midpoint, this role pays about $163k versus about $171k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 394 open roles on FindRole.

Listed pay typically runs $164,000–$246,000 across 394 roles with salary data.

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At a glance

TL;DR · Staff ATE Test Engineer, High-Speed I/O & Test Infrastructure

Staff ATE Test Engineer – High-Speed I/O & Test Infrastructure will join the team to develop and advance wafer-sort test infrastructure on Advantest V93000 platforms using SmarTest 8. The role involves building common Base Test Programs, Test Shells, and scalable architectures for high-speed I/O and die-to-die interfaces across the full product lifecycle. Key responsibilities include developing test flows, performing first-silicon bring-up, characterization, and failure isolation while collaborating with cross-functional teams to improve yield and test time. The candidate must possess expertise in Java and additional languages like C++, Python, or Perl, alongside proficiency in Linux environments and ORE simulation tools. Technical domain knowledge includes SerDes, PCIe, CXL, UCIe, Ethernet, and chiplet architectures. This role solves critical manufacturing challenges by ensuring high-quality test coverage for next-generation microprocessor and chiplet products through advanced ATE programming and debugging.

What you'll do

  • Develop and integrate reusable wafer-sort Base Test Program and common Test Shell infrastructure.
  • Lead SmarTest 8 and Advantest V93000 test program development, debugging, validation, and production support.
  • Drive wafer-sort strategy for high-speed I/O and die-to-die interfaces including bring-up and characterization.
  • Integrate patterns, timing, levels, and debug capabilities into common test programs.
  • Troubleshoot complex interactions between silicon, test software, tester hardware, and manufacturing processes.
  • Define scalable architecture and coding practices to enable reuse across products and manufacturing sites.
  • Lead technical reviews, document architectural decisions, and mentor engineers across global teams.

What we're looking for

  • Bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Experience developing and debugging test programs on Advantest V93000 platforms using SmarTest 8.
  • Proficiency in Java and at least one additional language such as C++, Python, Perl, or shell scripting (preferred).
  • Experience developing test flows, methods, patterns, timing, levels, diagnostics, characterization plans, and manufacturing screens (preferred).
  • Experience leading or making significant architectural contributions to a Base Test Program, common Test Shell, or similar shared ATE infrastructure (preferred).
  • Linux or Unix proficiency, including revision control and disciplined software-release practices (preferred).
  • Experience with ORE or comparable offline simulation tools (preferred).
  • Experience validating and debugging high-speed SerDes, source-synchronous, memory, or die-to-die interfaces (preferred).

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