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Active Keyword: Verification Methodology Remove filter Clear all

11 of up to 20 (filtered)

SOC Verification and Methodology Engineer

Qualcomm

San Diego, CA 25 days ago $98,500–$147,700
Actively hiring Confirmed live yesterday Trusted Below market
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout
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SOC Verification and Methodology Engineer Staff

Qualcomm

San Diego, CA 30 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Trusted Below market
ASIC Design RTL to GDS Flow Virtuoso System Simulation Circuit Design Logic Design Synthesis Place and Route Verification Validation Scripting Hardware Architecture Software Architecture
4+ yrs exp
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SOC Verification and Methodology Engineer

Qualcomm

San Diego, CA 73 days ago $164,000–$246,000
Actively hiring Confirmed live yesterday Low trust Above market
SystemVerilog UVM ASIC Design SoC Architecture ARM AMBA Python Perl Pre-silicon Emulation UCIe CXL DSP DDR Tapeout
6+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

Beaverton, OR 125 days ago
Actively hiring Confirmed live yesterday Low trust
Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL
10+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

Waltham, MA 148 days ago $134,700–$249,500
Actively hiring Confirmed live 2 days ago Low trust Competitive pay
Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence
3+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

Beaverton, OR 148 days ago
Actively hiring Confirmed live yesterday Low trust
Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence
3+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

San Francisco, CA 148 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Above market
Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium ModelSim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence
3+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

Austin, TX 148 days ago
Actively hiring Confirmed live 2 days ago Low trust
Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium Modelsim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence
3+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

Waltham, MA 149 days ago $165,800–$292,400
Actively hiring Confirmed live yesterday Low trust Above market
Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL
10+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

San Francisco, CA 149 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Low trust Above market
Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL
10+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

Austin, TX 149 days ago
Actively hiring Confirmed live yesterday Low trust
Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL
10+ yrs exp
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